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New Zen microarchitecture details

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Interesting, Global Foundries is expanding production 20 percent... I wonder why 😀

https://dailygazette.com/article/2017/02/09/globalfoundries-will-expand-production

"We are having such great demand for our projects that we're increasing our 14-nanmometer capacity by 20 percent," said Steven Grasso, a GlobalFoundries spokesman.
Fab 8 is the only GlobalFoundries plant making 14-nm chips, and is where the company is working to develop an even smaller chip -- one with 7-nm circuits. The expansion will include installation of additional manufacturing tools, but no physical expansion, Grasso said.
"In the United States, GF plans to expand 14-nm FinFET capacity by an additional 20 percent at its Fab 8 facility, with the new production capacities to come online in the beginning of 2018," the company said in its statement.
Click to expand...
 
krumme said:
Dresdenboy. Tell more about the smt story 😉
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Just saw that while checking what we guessed back then. 😉

Well I didn't learn too much about that. Just that I heard they considered it and IIRC they abandoned the idea due to the resulting complexity of verification and validation. My take: it might take millions of cycles until you see a malfunction in early simulation, especially with simulation tools and hardware they had 15 years ago.
 
I take the premium price as beeing most off reality for base freq. 🙂

Not that the betting in general was spot on - far from. What would cytg111 write today? This was his comment.
"
* Cannonlake IPC
* 4.0 GHz / 5.0 GHz Turbo
* SMT is at CMT levels
* $99 for top model
* unicorns reclaim their caveland from north korea
"

This sarcasm prediction will perhaps end up as the most precise. Lol.
 
Glo. said:
Are you aware if there will be any mini-ITX AM4 motherboard at launch, and if you are, are you also familiar with what type of chipset they will have?
Click to expand...

No idea.
At least none of the ODMs have displayed any, so far.
I've only tested high-end / enthusiast targeted boards.
 
Glo. said:
Are you aware if there will be any mini-ITX AM4 motherboard at launch, and if you are, are you also familiar with what type of chipset they will have?
Click to expand...

I'm not sure if it will be available at launch, but the BioStar X370-GTN is supposed to be mini-ITX.
 
krumme said:
I take the premium price as beeing most off reality for base freq. 🙂

Not that the betting in general was spot on - far from. What would cytg111 write today? This was his comment.
"
* Cannonlake IPC
* 4.0 GHz / 5.0 GHz Turbo
* SMT is at CMT levels
* $99 for top model
* unicorns reclaim their caveland from north korea
"

This sarcasm prediction will perhaps end up as the most precise. Lol.
Click to expand...

Wouldnt that be great? 🙂. So far it looks way better than anything i had hoped for.. But lets not forget.. 18 days to go and either way id rather have a nice surprise than a dissapointment on my hands.. the hypetrain can go hyperloop real fast.. and who knows sometimes the hype is true? 🙂
 
Looks like the big dog 1800x will be under $500? Holy...well I can't say it. Fill in the blanks. Imagine a very profane and quite excited moonbogg splashing out obscenities in a desperate attempt to express himself. This is looking to be a VERY easy buy. No brainer here folks. Zen or go home. I might even use some of the money I save on Zen to make a nice Ryzen aluminum wall sign.
 
Are there any released papers yet about XFR's efficiency? What i mean by that is:

1st) Will there be a "roof" ? And that "roof" would be the temps or the GHz?

2nd) How big the difference in XFR's efficiency would be between a top air-cooler compared to an average water-cooling system?

3rd) Do we expect Raven Ridge to have XFR too?
 
otinane said:
1st) Will there be a "roof" ? And that "roof" would be the temps or the GHz?
Click to expand...
The roof is the power/temperature of it.

Pure Power => Reduces power for same performance.
Precision Boost => Given Pure Power, calculate same power for increased performance.
Extended Frequency Range => Given both Pure Power & Precision Boost, calculate more power for extended increase of performance.

Pure Power/Precision Boost = Given TDP (65W/95W)
Extended Frequency Range = User-controlled TDP (125W/150W/180W/220W/Unlimited)
otinane said:
3rd) Do we expect Raven Ridge to have XFR too?
Click to expand...
Yes.
otinane said:
2nd) How big the difference in XFR's efficiency would be between a top air-cooler compared to an average water-cooling system?
Click to expand...
This is up in the air. (what a pun!)
 
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Thanks for the clarifications.

I wrote the question to look "stupid", because at first i had a suspicion that the whole XFR thing, could be just a stepping process or such.

Meaning:

Step 1.
increase (volt?frequency?core use?) a% -> check temp -> < A degrees (true?false?)
Step 2.
(true)
increase (volt?frequency?core use?) a/2% -> check temp -> < X degrees (true?false?)
(false)
decrease (volt?frequency?core use?) a/4% -> check temp -> < A degrees (true?false?)

etc

Until it stabilizes at a maximum, based on cooling method.
 
Doom2pro said:
Interesting, Global Foundries is expanding production 20 percent... I wonder why 😀
Click to expand...
22FDX will be at three+ foundries by 2020: Dresden, Chengdu, Malta (GlobalFoundries Triad), Shanghai (Shanghai Huali Microelectronics Corp).

"…developing a 22nm process in Malta for manufacturing in Dresden." <-- 22FDX

112,000(Dresden 2020) + 85,000(Chengdu 2020) + 60,000(Malta 2020) + 40,000(Shanghai 2020): 297,000 wafers out of the 400,000 FD-2D wafers from SOITEC.

22FDX-UHP has disappeared from the website. Note that 28nm SHP, nor had 28nm HPA ever appeared on GlobalFoundries website. So, what is GlobalFoundries doing with the planar successor to 28nm SHP(Kaveri/Godaveri)/A(Carrizo/Bhavani/Carrizo-L)/HPA(Bristol/Stoney)?
 
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Dresdenboy said:
...Cut...
Click to expand...
Sorry for asking this question, but I have stumbled across your post on another forum:
http://semiaccurate.com/forums/showpost.php?p=282456&postcount=6707

I know how that may sound, despite the fact that Apple cores are 2C/2T setups, but what you have said there, is extremely similar to Apple implementation of Macroscalar idea.
http://www.patentlyapple.com/patent...cture-will-it-take-ios-to-the-next-level.html
http://www.zdnet.com/article/apples-macroscalar-architecture-what-it-is-what-it-means/
The macroscalar processor addresses this problem in a new way: at compile-time it generates contingent secondary instructions so when a data-dependent loop completes the next set of instructions are ready to execute. In effect, it loads another pipeline for, say, completing a loop, so the pipeline remains full whether the loop continues or completes. It can also load a set of sequential instructions that run within or between loops, speeding execution as well.

The macro piece is the large number of program registers required so that all or most possible instruction paths are already loaded into CPU registers for fast execution. Instead of maintaining 1 pipeline, the architecture effectively maintains parallel pipelines, loading them and then switching between them to maximize loop performance.

Much of the patent is focused on compiler coding needed to take advantage of the macroscalar architecture. Essentially the compiler needs to analyze the work flow and understand where run-time decisions will be made so the processor can know when it needs an alternate pipeline.
Click to expand...
Keller with the design team, could've "moved" this into SMT. It may not be directly the same thing one to one, but it appears to be very similar in what it does.
 
Glo. said:
Sorry for asking this question, but I have stumbled across your post on another forum:
http://semiaccurate.com/forums/showpost.php?p=282456&postcount=6707

I know how that may sound, despite the fact that Apple cores are 2C/2T setups, but what you have said there, is extremely similar to Apple implementation of Macroscalar idea.
http://www.patentlyapple.com/patent...cture-will-it-take-ios-to-the-next-level.html
http://www.zdnet.com/article/apples-macroscalar-architecture-what-it-is-what-it-means/
Keller with the design team, could've "moved" this into SMT. It may not be directly the same thing one to one, but it appears to be very similar in what it does.
Click to expand...
This is interesting stuff! But given the overhead and compiler dependency I think this is too big of a change for a high frequency design (Zen level, no speed demon). A lower clocked design (like Apples AArch64 cores) might work with all the increased access/control delays per pipeline stage. Required recompilation works best in a controlled environment like Apple's.

For it to be used by AMD might be too risky. BD is able to run >20% faster in some recompiled benchmarks.

Applying this to Zen's SMT implementation would have left some traces in the microarchitecture and I think, it would be a heavy task to do that. The same is true for the upcoming Zen generations. And as it comes with a risk, while shifting the core's balance, adding logic, increasing delay and power consumption, they very likely would never have tried to do that with Zen.
 
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