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NostaSeronx
Diamond Member
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- Viewing thread Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
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NNostaSeronx replied to the thread Discussion AMD's Future APU Gone ARM?.Standard core option <-- Been here since Zen1 Dense core option <-- Been here since Zen4 Low Power core option <-- Will be added with...
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NNostaSeronx replied to the thread Discussion AMD's Future APU Gone ARM?.January 2016+ is when AMD got the Cat cores out of exclusivity with GlobalFoundries. May 2015 => GlobalFoundries kills 20nm July 2015...
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NNostaSeronx replied to the thread Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel).GlobalFoundries Malta 2023 going into Q4: ~20k average active wpm for 12LP family nodes ~15k average active wpm for 45SOI family nodes...
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NNostaSeronx replied to the thread Discussion Future ARM Cortex + Neoverse µArchs Discussion.The lack of SMT in client won't be significant enough for gaming. Vulkan/DX12 gaming leans more to SMT=Off having the highest FPS. ARM...
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NNostaSeronx replied to the thread Discussion RISC V Latest Developments Discussion [No Politics].Under '卓越的CPU性能' "单核CPU算力领先ARM A55 30%以上" "leads ARM A55 by more than 30%" Under '领先的算力能效' "RISC-V架构的精简和卓越的微架构设计，算力能效比ARM A55高20%以上"...
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NNostaSeronx replied to the thread Discussion AMD's Future APU Gone ARM?.Alastor D6 (Zen4 target core) has this partition: The current iteration supposedly can support THREE of these Aegis clusters on a...
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NNostaSeronx replied to the thread Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000).Xiaolong is the chinese name for EPYC not Hygon-related. Hygon switched to RISC-V after: "However, in [June] 2019, the U.S. Department...
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NNostaSeronx replied to the thread Discussion RISC V Latest Developments Discussion [No Politics].Overall that isn't an issue now going forward. As the XT910/C910 was a wild-west pre-[riscv-profiles] core. While the C920 is a...
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NNostaSeronx replied to the thread Discussion RISC V Latest Developments Discussion [No Politics].The current designs out are VEC > OoO Int/Fp. The best case workloads are stuff that do not require strong cores. The bare minimum to...
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NNostaSeronx replied to the thread Discussion RISC V Latest Developments Discussion [No Politics].C910's B-ext is loaded in custom opcode. As well as no V-ext support w/ rollback support from geekbench. GB5 - Single core: C910 vs...
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NNostaSeronx replied to the thread Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel).January 2024: Canon is expected to ship NZ2C machines this year. For 1/10th the cost of EUV: Low-NA: $1xx million tool => NIL: $1x.x...
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NNostaSeronx replied to the thread Discussion RISC V Latest Developments Discussion [No Politics].Been going through the later RISC-V events: Two P550 boards in the 1st Half and One P670 board in the second half. As well as some of...
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NNostaSeronx replied to the thread Discussion RISC V Latest Developments Discussion [No Politics].Nothing. The CPU would be manufactured in North America for the Non-GC market. If Intel/Samsung/GlobalFoundries is inserting "chip in...
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NNostaSeronx replied to the thread Discussion RISC V Latest Developments Discussion [No Politics].Tenstorrent(NotCN) is likely to be on Samsung's SF4X. They haven't announced any GPU partners yet. Ventana(NotCN) is likely to be on...
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NNostaSeronx replied to the thread Discussion RISC V Latest Developments Discussion [No Politics].From last August (August 2023): -Tenstorrent - 2x Big Core + 4x Small Core configuration. For "Mobile" solutions. (Like: PHX2/Z1.)...
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