ashFTW
Senior member
- Sep 21, 2020
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I'm repeating myself a lot, but perhaps this helps...
We can break this discussion down to two questions. Let's answer the first one, and then answering the second becomes much easier.
Question 1. Intel has only publicly discussed the 400 mm2 XCC SPR tile with 15 cores each. Four of these are combined together with EMIB to make the SPR chip with (up to) 60 cores. It's not currently publicly known how Intel plans to make lower core count (8/12/16 etc) SPR chips. For example, how will intel make something like the 16 core IceLake Xeon Silver 4314 with a full complement of PCIe lanes and memory channels (but reduced cache), which has an MSRP of only $750?
Option 1: Since only 1/4th the I/O and memory is on each SPR tile, four XCC SPR tiles could be used. Note that these tiles can have defective/fused-off cores but no unrecoverable defects in the I/O, memory, and EMIB PHY areas. There are also 10 additional EMIB tiles (totaling 215 mm2 **), as well as the added costs of advanced packaging. Given that lower end chips have a much larger volume and low MSRP, this option as the only option, is complete madness! Intel may be forced to use this option to satisfy some portion of the low-core parts volume, or for SKUs with full L3 cache, but using this option exclusively would be a colossal money loosing proposition.
Intel 7 yield issues have been brought up before to support this option. But Intel 7 is making half this size die in high volume Alder/Raptor lake parts with no problem. And with extensive block repair/recovery methods, with 74% of the chip being recoverable, a large portion of the SPR tiles will be functional. Intel has also been selling 470 and 628 mm2 Icelake Xeon parts in high volume but on a slightly older 10nmSF.
** Estimated from the figure below from IEEE ISSCC 2022. Also note that EMIB takes over 1/8th of the SPR tiles.
Option 2: Keep the 4 tile design, but make the tiles smaller with reduced number of cores. Let's remove two rows of cores (total 8) per tile. Now we have 7 cores per tile, and 28 core parts with all cores functioning. We do have all the I/O and memory, but we also still have the complexity of the 4 tile design. The Silicon savings are there of course. I estimate that these tile will be 250 mm2 or so. Two fewer EMIB tiles will be needed, but over 17% of the 1000 mm2 is now dedicated to die-to-die fabric.
Option 3: Build a monolithic die for lower core counts. For example, take one of the 15 core tiles and add 1-2 rows of cores. Use the area now dedicated to EMIB PHYs to add additional I/O and memory. Option 3 is superior to Option 2, because it's much simpler and cheaper to make, while still reusing large parts of the design. The size should be 450-500 mm2. This option also better covers the even lower core count (like 8 and 12) SKUs. With no multi-die fabric, the chip should perform better as well.
I have no insider information, but to me Option 3 makes the most sense for Sapphire and Emerald Rapids. Granite Rapids and Falcon Ridge are disaggregated with separate compute only tiles, in which case the number of cores can be scaled by just adding more (preferred) or bigger compute tiles.
Question 2. How will Intel make SPR workstations chips?
For a high core count professional workstation (say with 48-60 cores) 4 x XCC is the only option.
For a low core count enthusiast workstation with 16-24 cores and half the I/O and memory channels, my answer would be to use the monolithic die from Option 3 above, though 2 x XCC would also be fine here as @nicalandia has suggested. Or it could be a combination of the two, but being low volume product, that's unlikely.
This is not a competition, let's wait and see what Intel does.
We can break this discussion down to two questions. Let's answer the first one, and then answering the second becomes much easier.
Question 1. Intel has only publicly discussed the 400 mm2 XCC SPR tile with 15 cores each. Four of these are combined together with EMIB to make the SPR chip with (up to) 60 cores. It's not currently publicly known how Intel plans to make lower core count (8/12/16 etc) SPR chips. For example, how will intel make something like the 16 core IceLake Xeon Silver 4314 with a full complement of PCIe lanes and memory channels (but reduced cache), which has an MSRP of only $750?
Option 1: Since only 1/4th the I/O and memory is on each SPR tile, four XCC SPR tiles could be used. Note that these tiles can have defective/fused-off cores but no unrecoverable defects in the I/O, memory, and EMIB PHY areas. There are also 10 additional EMIB tiles (totaling 215 mm2 **), as well as the added costs of advanced packaging. Given that lower end chips have a much larger volume and low MSRP, this option as the only option, is complete madness! Intel may be forced to use this option to satisfy some portion of the low-core parts volume, or for SKUs with full L3 cache, but using this option exclusively would be a colossal money loosing proposition.
Intel 7 yield issues have been brought up before to support this option. But Intel 7 is making half this size die in high volume Alder/Raptor lake parts with no problem. And with extensive block repair/recovery methods, with 74% of the chip being recoverable, a large portion of the SPR tiles will be functional. Intel has also been selling 470 and 628 mm2 Icelake Xeon parts in high volume but on a slightly older 10nmSF.
** Estimated from the figure below from IEEE ISSCC 2022. Also note that EMIB takes over 1/8th of the SPR tiles.
Option 2: Keep the 4 tile design, but make the tiles smaller with reduced number of cores. Let's remove two rows of cores (total 8) per tile. Now we have 7 cores per tile, and 28 core parts with all cores functioning. We do have all the I/O and memory, but we also still have the complexity of the 4 tile design. The Silicon savings are there of course. I estimate that these tile will be 250 mm2 or so. Two fewer EMIB tiles will be needed, but over 17% of the 1000 mm2 is now dedicated to die-to-die fabric.
Option 3: Build a monolithic die for lower core counts. For example, take one of the 15 core tiles and add 1-2 rows of cores. Use the area now dedicated to EMIB PHYs to add additional I/O and memory. Option 3 is superior to Option 2, because it's much simpler and cheaper to make, while still reusing large parts of the design. The size should be 450-500 mm2. This option also better covers the even lower core count (like 8 and 12) SKUs. With no multi-die fabric, the chip should perform better as well.
I have no insider information, but to me Option 3 makes the most sense for Sapphire and Emerald Rapids. Granite Rapids and Falcon Ridge are disaggregated with separate compute only tiles, in which case the number of cores can be scaled by just adding more (preferred) or bigger compute tiles.
Question 2. How will Intel make SPR workstations chips?
For a high core count professional workstation (say with 48-60 cores) 4 x XCC is the only option.
For a low core count enthusiast workstation with 16-24 cores and half the I/O and memory channels, my answer would be to use the monolithic die from Option 3 above, though 2 x XCC would also be fine here as @nicalandia has suggested. Or it could be a combination of the two, but being low volume product, that's unlikely.
This is not a competition, let's wait and see what Intel does.
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