- Feb 27, 2003
Obviously we don't know if zen6 is going to be on AM5, but the continued socket changing definitely wants me to stay with AMD.
So, what I've heard of MTL desktop is...weird, and I'm not sure I've any leak quite in alignment. That said, my info might very well be out of date, but I'm ultimately quite curious what Intel decides to do. Timing of Arrow Lake is probably critical.Yes desktop haha.
I'm not nearly so optimistic for Intel. Obviously graphics will be a huge win for AMD, but they also have a full node jump + new architectures going for them on the CPU side. The efficiency gap is going to be pretty darn stark, and Intel's battery life numbers are bad enough as it is. I can't believe they actually regressed from Tiger Lake.I don't think the CPU comparisons will be bad, at least performance. The GPU is a problem.
So, I get what you're saying here, but it would definitely be better for Intel to have Meteor Lake come out ASAP, and deal with any consequences to Raptor Lake or whatever. I consider myself a bit of an MTL pessimist, but it's still going to be a significant improvement over RPL, and I imagine the fabs are begging for something on Intel 4/3 to ramp with.But it doesn't really matter if Raptorlake mobile is having a comprehensive lineup. Then Meteorlake mobile is going to come 12 month later, period. [snip]
I dislike the naive application of the square root law here, as clearly there are many different designs in the market, some of which are strictly superior to others, and I think that's the root of my argument - the differences in the underlying engineering investment.It's always a tradeoff. So apples-to-apples the square root law says 30% performance needs a core that's 70% larger. Also the single core focused design will have higher frequencies, so that'll result in the core larger as well.
So, I admittedly took something of a leap here. The actual info I'm working with is the claim that IDC's best engineers (and the majority in general) rolled off from Golden Cove to Lion Cove, meaning that Redwood Cove and especially Raptor Cove get the scraps. Therefore, my logic goes, surely the IPC gains from either won't be competitive with Golden Cove. Plus, I've heard that a lot of effort on Lion Cove is focused on "modernizing" it. I'm still uncertain what numbers that will translate to for IPC, freq, etc., but the implication was that it's a painful, if necessary adjustment, so I interpreted it as a negative modifier. In any case, I do think that MLID's >30% number is too high. When's the last time any company achieved that gen/gen? Hah, then again, I guess I have hyped up LNC a bit myself.It's not small. Here's what Raichu said:
Some are expecting Haswell-like gains, which is low 10%. 12% seems to be a good average. Haswell was also efficiency focused, so some have said they reduced potential performance to lower power.
Maybe they are doing small/Medium gains rather than zero/Large gains they are doing now. Sunny = Large, Willow = tiny/zero, Golden = Large
Raptor = small, Redwood = Medium, etc. Which would be better for planning I guess?
Maybe Intel will petition Congress to rescind Amdahl's Law.
Handbrake comes to mind. Its scaling diminishes beyond a certain number of cores. I would certainly rather have 12-16P cores to commit to it than a bunch of e-cores. Also I would much rather have 16P cores for a unified gaming + streaming box.Have we legitimately seen a DESKTOP consumer grade application that would really benefit from having more than 8 P cores as opposed to having 4 times as many additional E cores?
yeah. Hard pass as far as i am concerned. Gimme 16 + 16 instead of 8 + 32 and then i might be interested.
Don't think it was just MLID that expected that gain. Pretty much everyone did. Maybe there was a confusion between total performance versus architectural.Plus, MLID has a pretty terrible track record with IPC claims, and usually overshoots. We're seeing that play out right now in the Zen 4 thread.
12-21% IPC increase for MTL over RPL? Locuza and Semianalysis already did a great die shot analysis of MTL. It seems there were few changes to the core, so doesn't that make this IPC prediction completely impossible?
I've seen MLID be proved wrong many times before, but never as soon as he made the prediction 😆
How big do you think a 24c/8ch/4xIO monolithic die would be? The problem is that 10 nm yield is still very mediocre to the point where you'd have to slash the core count way down to the point where it wouldn't really be viable as a Metal Xeon.SPR on the other hand, since it only has a 1/4th subset of memory controllers, PCIe, CXL, UPI on each of the tiles, they cannot make a chip with full IO unless all 4 chiplets are used. That makes sense for large core count parts. For smaller core counts it’s much cheaper to make monolithic. It would be a disaster if they had to use 1600 mm2 silicon (not counting the EMIB tiles) for every SKU, some of them may even go as low as 8/12/16 cores. Keeping the 4 chiplet design for lower core count also doesn’t make sense, because if you decide to make smaller “1/4th split chiplets”, you might as well make a monolithic which will be far cheaper to make. Intel in the past has made several different size Xeon chips to address the core count range — XCC, MCC, LCC. So they are likely to make several size chips; they do not have the financial constraints to only make one tile (and it’s mirror) for SPR.
Not sure about you...
Then again, you could have say 24 of those high IPC cores, with only say 8 of them boosting to 5+ GHz while gaming, and then most/all of them running on lower clocks for highly-threaded apps and very likely be significantly faster than Xeon 3175x, and not just its equivalent. As a bonus, you could get away with all the little.big core scheduling shenanigans or lack of AVX-512 for the same reason.Not sure about you...
But 8 P-cores with High IPC for gaming and the equivalent of a Xeon W-3175X for highly threaded apps on a Single CPU sounds like a Fine CPU to me.
That is a very powerful CPU, we are talking about a CPU that will likely match or beat a Zen3 ThreadRipper 5975WX in MT workloads.
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Can I just say that it is kind of amazing that someone was able to take pictures of wafers on a show floor of a high enough quality that we can not only determine die sizes, but do so even for the various functions on the die!There is a good analysis from Cardyak on this topic. Redwood is more focused on integer upgrades.
And he also "leaked" socket LGA2551 photo which clearly based on the photo is a BGA type of socket.Thanks. Was on mobile at the time. Didn't want to scrub through a video. Or give it a view, tbh. And quality is plenty fine.
So I'll just give my take item by item.
- Socket - No clue. I thought MTL/ARL would use LGA
18001700 (Edit: Typo?), but I also knew they would not be platform compatible with ADL/RPL. Could see this being true, but little difference either way. Though a new socket typically hurts motherboard prices.
- IPC - Bull. Maybe bigger than Raptor Lake, but 12-21%? Nah, he's just making stuff up.
- Clock speed regressions - Probably bull. Maybe they'll lose 100-200MHz or so, but large enough to compare to ICL? Nah. I fully expect the node shrink to make up any regression from arch/design, and personally guess that clocks will ultimately be higher between comparable SKUs.
- VPU - sure
- 2+8, 6+8 - sure, 8+16 - no
- RPL/MTL volume split - Not sure, but certainly suspicious.
- Timing - Sounds reasonable enough.
- 8+32 on 20A - Think so?
- LNC IPC - I'm thinking comparable-ish to Golden Cove's gains. Expecting >>GLC gains (like his previous "at least 30%" claim) is just nonsense. But make no mistake, LNC is probably the most important evolution of Core since its inception. Much better in a whole host of ways.
- Lion Cove is not Royal. Royal is Royal. How hard is this to understand? Clearly no clue what he's talking about.
- Skymont - We're in for a treat with this one.
- Timing - Sounds reasonable enough.
In short, I think all the "new", important details range from suspect to nonsensical, and the rest just reiterating well established rumors.
28 core Icelake Xeon is around 470 mm2 **, and is shipping in high volume along with its bigger sibling, as has been said by Intel management on their earning calls. I expect SPR 24 core chip to be around the same size, maybe a tad smaller like 450 mm2. SPR is on Intel 7, an improved 10nm compared to ICL. Alder and Raptor Lake are also on Intel 7. Raptor will probably be half the size of the above monolithic SPR, which is again going to be produced in large volume.How big do you think a 24c/8ch/4xIO monolithic die would be? The problem is that 10 nm yield is still very mediocre to the point where you'd have to slash the core count way down to the point where it wouldn't really be viable as a Metal Xeon.
Can I just say that it is kind of amazing that someone was able to take pictures of wafers on a show floor of a high enough quality that we can not only determine die sizes, but do so even for the various functions on the die!
And thanks to that we are able to further guesstimate future Products based on this info.Can I just say that it is kind of amazing that someone was able to take pictures of wafers on a show floor of a high enough quality that we can not only determine die sizes, but do so even for the various functions on the die!
I crudely did it out, based upon the available SPR tile shot, and got 719 mm2, lol. 428 mm2 for 24 cores and the memory tiles, 228 mm2 for 4xIO and 63 for 4xmemory controllers. That can't be right but surely that's closer than your estimate. Golden Cove Server is a lot bigger than Client because of AMX and the extra AVX-512 unit.I expect SPR 24 core chip to be around the same size, maybe a tad smaller like 450 mm2. SPR is on Intel 7, an improved 10nm compared to ICL.
24 cores would take an insane amount of space, even on the latest process from TSMC.Then again, you could have say 24 of those high IPC cores, with only say 8 of them boosting to 5+ GHz while gaming, and then most/all of them running on lower clocks for highly-threaded apps and very likely be significantly faster than Xeon 3175x, and not just its equivalent.
So he's saying it can get 20% gain for Integer but much less for FP? When they say "Integer" it means basically overall perf/clock improvement. It's like increasing the speed limit of the highway and widening it. It benefits every block that uses it, not just "integer". Branch prediction, ROBs, OoOE blocks, L/S units, micro op cache, all benefit all code. It's not like FPU is on a separate block connected by a ring bus.There is a good analysis from Cardyak on this topic. Redwood is more focused on integer upgrades.
Just be prepared to be disappointed when Intel officially announces Sapphire Rapids for Workstations.So my conviction stands as before -- 1 (maybe even 2) SPR monolithic die at the lower core count end
24 P-Cores on a world where thermals don't matter would get 56,000 points in CB R23, a realistic 8 P + 32 E configuration gets you 50,000+ points in CB R23(as estimated by Puget Systems)24 cores would take an insane amount of space, even on the latest process from TSMC.
24P cores is actually roughly equal to 8 P and almost 64 E cores not 32.
Just to be clear, do you mean Lion Cove or Redwood Cove here? I'm inclined to believe that Raichu is correct, and that Redwood Cove is more efficiency focused. I think Lion Cove is a much better opportunity from a performance perspective, but I think they're going to be careful to balance power and area as well.Yea I don't know about Lion Cove. Maybe the efficiency gain will be great, but the absolute performance gain for the uarch is Golden Cove level. Like when we look at Haswell, it was great for laptops, but performance-wise? Not much.
Well I expect Royal to be far, far beyond a mere +30%, but that's worth a thread in its own right. Maybe will make one if anything of substance actually leaks.20% gain takes amazing amount of enhancement and additions to get there. 30% takes a serious, almost forced flaw in the predecessor to happen.
I am very unimpressed with this take, and think they're basically just reading the tea leaves and pulling actual numbers out of thin air. They have no idea what individual changes actually consist of, and while I can admire effort being spent into analyzing the information we have, I'm considerably colder towards any attempts to make confident assertions about the results.There is a good analysis from Cardyak on this topic. Redwood is more focused on integer upgrades.
Some people say the LGA2551 picture from MLID belongs to BGA2551 and is likely the successor of BGA1964 (ADL-HX, basically ADL-S on BGA). If you say 8+16 won't exist and assuming it's true it's doesn't seem like MTL-S is able to replace the upcoming 13900k.
I am addressing your whole post, so yes I'm talking about Lion Cove.Just to be clear, do you mean Lion Cove or Redwood Cove here? I'm inclined to believe that Raichu is correct, and that Redwood Cove is more efficiency focused. I think Lion Cove is a much better opportunity from a performance perspective, but I think they're going to be careful to balance power and area as well.
Yea and 8+32 would take way less space and power. 8+32 = 1624 P-Cores on a world where thermals don't matter would get 56,000 points in CB R23, a realistic 8 P + 32 E configuration gets you 50,000+ points in CB R23(as estimated by Puget Systems)
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