Discussion Intel current and future Lakes & Rapids thread

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Redfire

Redfire

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May 15, 2021
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jpiniero said:
The mainstream line has always had an ECC option in the name of Xeon E3/E. There's a reason they didn't do Xeons for Alder Lake. That they would put a single tile SPR on LGA 1700 and call that Xeon E makes the most sense.
Click to expand...

Xeon-E is only launched for every other consumer generation. They didn't do one for Alder Lake because they launched one for Rocket Lake already.
CFL-R : Mehlow (Xeon E-22XX)
RKL-S : Tatlow (Xeon E-23XX)
RPL-S : Catlow (Xeon E-24XX?)


gdansk said:
Just to be clear: the non-Xeon Alder Lake chips support ECC in W680 boards now. Why would they even need a LGA1700 Xeon anymore? Is a single SPR tile going to be that much more capable?
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Support for ECC in regular Alder Lake chips replaces what was previously the Xeon W-1000 series, not the Xeon-E series. I'm not actually sure what the difference between the two is, but they're two separate product lines.


DrMrLordX said:
Something about Sapphire Rapids is broken. Cross your fingers and hope that they are at least able to ship some limited quantity now, and that they will get it shipping soon. Emerald Rapids, as sad as it may be, is little more than Sapphire Rapids with some improvements. Given how long Sapphire Rapids has been in development, it's entirely possible that Emerald Rapids may be close behind it, once Intel fixes the problems fundamental to tile-based server CPUs on 10ESF. It would really be better for Intel to mostly skip over Sapphire Rapids and move to the refresh product if possible.
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Sapphire Rapids hasn't had an "excessive" amount of issues on a chip-level as far as I'm aware. Most of the issues have been related to the platform and validation. I don't believe it's a "fundemental" problem with tile-based CPUs on Intel 7. Emerald Rapids is coming out at earliest, in Q1-2023, quite a bit after Sapphire Rapids.
 
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jpiniero

Lifer
Oct 1, 2010
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Redfire said:
Xeon-E is only launched for every other consumer generation. They didn't do one for Alder Lake because they launched one for Rocket Lake already.
CFL-R : Mehlow (Xeon E-22XX)
RKL-S : Tatlow (Xeon E-23XX)
RPL-S : Catlow (Xeon E-24XX?)
Click to expand...

No, they just didn't do one for Comet Lake, only Xeon W. Every gen previous to that has had one (which goes back to Xeon E3).
 
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Timmah!

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Jul 24, 2010
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Saylick

Saylick

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Sep 10, 2012
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Timmah! said:
What is on the second picture? What are the "wings" on the side of SPR with HBM? Does those contain the same stuff, which is on the sides of regular non-HBM SPR, but here does not fit, cause of the HBM? Does that mean different socket?
Click to expand...
The 2nd picture is a high-density package version of Meteorlake.
Just a guess: the "wings" on the side of the SPR w/ HBM are likely just additional substrate area for all of the stuff that got pushed out of the way due to the 4 stacks of HBM, which includes the capacitors and that FPGA die that was on the side of the non-HBM version of SPR.
 
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dullard

dullard

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May 21, 2001
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Saylick said:
I can only assume the tiles align with Intel's presentation:
Click to expand...
The SOC tile does match up with their presentation cartoons. But the question stems from the odd size of that large tile if it is the SOC. Alder Lake's SOC is just under 50 mm^2. The photos from Meteor Lake show a large tile just over 100 mm^2. If the large tile is the SOC, then why did it double in size? Someone in this thread hinted that there are also unannounced CPU cores in the SOC (in addition to the CPU tile)--but said so with no public evidence. I can't buy that until there is some sort of evidence. Or maybe Intel is adding something else that we don't yet know. Or Intel is using up old node capacity, but that seems highly doubtful.

The argument for it being the GPU is that it fits the rumored 192 EUs pretty well. 192 EUs is 6 times the 32 EUs of Alder Lake. The big tile is triple the size of Alder Lake's GPU. So, if Intel can find a node that is twice as dense as Intel 7 then it would perfectly fit the rumored 192 EUs.
 
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jpiniero

Lifer
Oct 1, 2010
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dullard said:
The SOC tile does match up with their presentation cartoons. But the question stems from the odd size of that large tile if it is the SOC. Alder Lake's SOC is just under 50 mm^2.
Click to expand...

Are you including the IO that's on the CPU die AND the PCH?
 
DrMrLordX

DrMrLordX

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Apr 27, 2000
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Saylick said:
I can only assume the tiles align with Intel's presentation:
Click to expand...

That SoC tile is huge!

jpiniero said:
Meteor Lake is only 2+8? I was kind of expecting them to increase the core count.
Click to expand...

There should be a 6+8 compute tile.

dullard said:
The SOC tile does match up with their presentation cartoons. But the question stems from the odd size of that large tile if it is the SOC.
Click to expand...

Exactly! What did they put in there to make it so big?
 
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igor_kavinski

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Jul 27, 2020
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DrMrLordX said:
Exactly! What did they put in there to make it so big?
Click to expand...
Maybe it's just for illustration. That looks like a very weird chip to cool. CPU and GPU would produce more heat than the other two tiles, making the heat production very disproportionate in relation to the total available surface area.
 
dullard

dullard

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May 21, 2001
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igor_kavinski said:
Maybe it's just for illustration. That looks like a very weird chip to cool. CPU and GPU would produce more heat than the other two tiles, making the heat production very disproportionate in relation to the total available surface area.
Click to expand...
It could be just for illustration, but they did go and make a physical tiled chip to let people photograph. That seems like a lot of work for an illustration. Since these publically shown examples are theoretically mobile or even ultramobile chips, there isn't that much heat to dissipate.

1652301132632.png
 
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E

Exist50

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Aug 18, 2016
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Saylick said:
I can only assume the tiles align with Intel's presentation:
Click to expand...
That would be a perfectly reasonable assumption. Unfortunately, reasonable does not mean correct, in this case.

I've said it before, but the big center die is SoC, right is GPU, upper left is CPU, and lower left is additional IO.

dullard said:
If the large tile is the SOC, then why did it double in size? Someone in this thread hinted that there are also unannounced CPU cores in the SOC (in addition to the CPU tile)--but said so with no public evidence. I can't buy that until there is some sort of evidence. Or maybe Intel is adding something else that we don't yet know.
Click to expand...
It's more than just the PCH. It's basically everything except (most) CPU cores, GPU cores, and a little bit of the IO.

dullard said:
The argument for it being the GPU is that it fits the rumored 192 EUs pretty well. 192 EUs is 6 times the 32 EUs of Alder Lake.
Click to expand...
I think the GPU in these images is 64EU (maybe 32?). Not 100% sure though. But definitely not 192EU, at any rate.
 
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jpiniero

Lifer
Oct 1, 2010
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Exist50 said:
I think the GPU in these images is 64EU (maybe 32?). Not 100% sure though. But definitely not 192EU, at any rate.
Click to expand...

Figure it has to be 96 at the very least. Remember it's supposedly using N3. While dumb, it does mean that it would be a double shrink+ compared to where they are now.
 
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mikk

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2+8 is MTL-M, this SKU might not get 192 EUs. Pretty sure we will see a bigger GPU segmentation in this generation, even though I hope it's not a poor AMD segmentation where mainly dGPU SKUs get the fastest iGPU and the more useful iGPU SKUs for thin and light devices are downgraded.
 
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Exist50

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jpiniero said:
Figure it has to be 96 at the very least. Remember it's supposedly using N3. While dumb, it does mean that it would be a double shrink+ compared to where they are now.
Click to expand...
Where do you see N3 for MTL? And I think it's just too small to be anything more than 64EU.
 
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NostaSeronx

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Last edited:
DrMrLordX

DrMrLordX

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The planned 2022 Meteor Lake was supposedly going to use N5 for iGPU tiles. No idea what Intel will be doing what with the delay to 2023.
 
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