No, they just didn't do one for Comet Lake, only Xeon W. Every gen previous to that has had one (which goes back to Xeon E3).
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Discussion Intel current and future Lakes & Rapids thread
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No, they just didn't do one for Comet Lake, only Xeon W. Every gen previous to that has had one (which goes back to Xeon E3).
coercitiv
Diamond Member
Did we find out eventually what the 4th tile is used for on MTL?
What is on the second picture? What are the "wings" on the side of SPR with HBM? Does those contain the same stuff, which is on the sides of regular non-HBM SPR, but here does not fit, cause of the HBM? Does that mean different socket?
Saylick
Diamond Member
Saylick
Diamond Member
The 2nd picture is a high-density package version of Meteorlake.
Just a guess: the "wings" on the side of the SPR w/ HBM are likely just additional substrate area for all of the stuff that got pushed out of the way due to the 4 stacks of HBM, which includes the capacitors and that FPGA die that was on the side of the non-HBM version of SPR.
dullard
Elite Member
The SOC tile does match up with their presentation cartoons. But the question stems from the odd size of that large tile if it is the SOC. Alder Lake's SOC is just under 50 mm^2. The photos from Meteor Lake show a large tile just over 100 mm^2. If the large tile is the SOC, then why did it double in size? Someone in this thread hinted that there are also unannounced CPU cores in the SOC (in addition to the CPU tile)--but said so with no public evidence. I can't buy that until there is some sort of evidence. Or maybe Intel is adding something else that we don't yet know. Or Intel is using up old node capacity, but that seems highly doubtful.
The argument for it being the GPU is that it fits the rumored 192 EUs pretty well. 192 EUs is 6 times the 32 EUs of Alder Lake. The big tile is triple the size of Alder Lake's GPU. So, if Intel can find a node that is twice as dense as Intel 7 then it would perfectly fit the rumored 192 EUs.
Are you including the IO that's on the CPU die AND the PCH?
DrMrLordX
Lifer
That SoC tile is huge!
There should be a 6+8 compute tile.
Exactly! What did they put in there to make it so big?
dullard
Elite Member
I assumed that was on the IO tile.
igor_kavinski
Lifer
Maybe it's just for illustration. That looks like a very weird chip to cool. CPU and GPU would produce more heat than the other two tiles, making the heat production very disproportionate in relation to the total available surface area.
dullard
Elite Member
It could be just for illustration, but they did go and make a physical tiled chip to let people photograph. That seems like a lot of work for an illustration. Since these publically shown examples are theoretically mobile or even ultramobile chips, there isn't that much heat to dissipate.
That would be a perfectly reasonable assumption. Unfortunately, reasonable does not mean correct, in this case.
I've said it before, but the big center die is SoC, right is GPU, upper left is CPU, and lower left is additional IO.
It's more than just the PCH. It's basically everything except (most) CPU cores, GPU cores, and a little bit of the IO.
I think the GPU in these images is 64EU (maybe 32?). Not 100% sure though. But definitely not 192EU, at any rate.
I really wish people would stop quoting him. He's so far off base it's not even funny.
IntelUser2000
Elite Member
That was in an Intel presentation!
Figure it has to be 96 at the very least. Remember it's supposedly using N3. While dumb, it does mean that it would be a double shrink+ compared to where they are now.
2+8 is MTL-M, this SKU might not get 192 EUs. Pretty sure we will see a bigger GPU segmentation in this generation, even though I hope it's not a poor AMD segmentation where mainly dGPU SKUs get the fastest iGPU and the more useful iGPU SKUs for thin and light devices are downgraded.
Where do you see N3 for MTL? And I think it's just too small to be anything more than 64EU.
NostaSeronx
Diamond Member
I'm sort of crazy.
My interpretation based on all the rumors being bombarded all over.
CPU tile should be the smallest: https://videocardz.com/newz/first-die-shot-of-intel-14th-gen-core-meteor-lake-processor-emerges
Since, the same resources on Intel 7 is about ~40 mm2/~49 mm2. 2 P-cores+8 E-cores should be the smallest tile. I/O should basically not scale at all so should be associated with larger parts not smaller ones.
My interpretation based on all the rumors being bombarded all over.
CPU tile should be the smallest: https://videocardz.com/newz/first-die-shot-of-intel-14th-gen-core-meteor-lake-processor-emerges
Since, the same resources on Intel 7 is about ~40 mm2/~49 mm2. 2 P-cores+8 E-cores should be the smallest tile. I/O should basically not scale at all so should be associated with larger parts not smaller ones.
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nicalandia
Diamond Member
I suspect this is a Mobile version with very low power requirement.
Crestmont and Rewood Cove look identical to Gracemont and Golden Cove
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