Saylick
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- Sep 10, 2012
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Did we find out eventually what the 4th tile is used for on MTL?Looks like PC-Watch got some photos of Intel's upcoming products:
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IODid we find out eventually what the 4th tile is used for on MTL?
What is on the second picture? What are the "wings" on the side of SPR with HBM? Does those contain the same stuff, which is on the sides of regular non-HBM SPR, but here does not fit, cause of the HBM? Does that mean different socket?Looks like PC-Watch got some photos of Intel's upcoming products:
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The 2nd picture is a high-density package version of Meteorlake.What is on the second picture? What are the "wings" on the side of SPR with HBM? Does those contain the same stuff, which is on the sides of regular non-HBM SPR, but here does not fit, cause of the HBM? Does that mean different socket?
The SOC tile does match up with their presentation cartoons. But the question stems from the odd size of that large tile if it is the SOC. Alder Lake's SOC is just under 50 mm^2. The photos from Meteor Lake show a large tile just over 100 mm^2. If the large tile is the SOC, then why did it double in size? Someone in this thread hinted that there are also unannounced CPU cores in the SOC (in addition to the CPU tile)--but said so with no public evidence. I can't buy that until there is some sort of evidence. Or maybe Intel is adding something else that we don't yet know. Or Intel is using up old node capacity, but that seems highly doubtful.I can only assume the tiles align with Intel's presentation:
Are you including the IO that's on the CPU die AND the PCH?The SOC tile does match up with their presentation cartoons. But the question stems from the odd size of that large tile if it is the SOC. Alder Lake's SOC is just under 50 mm^2.
That SoC tile is huge!I can only assume the tiles align with Intel's presentation:
There should be a 6+8 compute tile.Meteor Lake is only 2+8? I was kind of expecting them to increase the core count.
Exactly! What did they put in there to make it so big?The SOC tile does match up with their presentation cartoons. But the question stems from the odd size of that large tile if it is the SOC.
I assumed that was on the IO tile.Are you including the IO that's on the CPU die AND the PCH?
Maybe it's just for illustration. That looks like a very weird chip to cool. CPU and GPU would produce more heat than the other two tiles, making the heat production very disproportionate in relation to the total available surface area.Exactly! What did they put in there to make it so big?
It could be just for illustration, but they did go and make a physical tiled chip to let people photograph. That seems like a lot of work for an illustration. Since these publically shown examples are theoretically mobile or even ultramobile chips, there isn't that much heat to dissipate.Maybe it's just for illustration. That looks like a very weird chip to cool. CPU and GPU would produce more heat than the other two tiles, making the heat production very disproportionate in relation to the total available surface area.
That would be a perfectly reasonable assumption. Unfortunately, reasonable does not mean correct, in this case.I can only assume the tiles align with Intel's presentation:
It's more than just the PCH. It's basically everything except (most) CPU cores, GPU cores, and a little bit of the IO.If the large tile is the SOC, then why did it double in size? Someone in this thread hinted that there are also unannounced CPU cores in the SOC (in addition to the CPU tile)--but said so with no public evidence. I can't buy that until there is some sort of evidence. Or maybe Intel is adding something else that we don't yet know.
I think the GPU in these images is 64EU (maybe 32?). Not 100% sure though. But definitely not 192EU, at any rate.The argument for it being the GPU is that it fits the rumored 192 EUs pretty well. 192 EUs is 6 times the 32 EUs of Alder Lake.
I really wish people would stop quoting him. He's so far off base it's not even funny.
That was in an Intel presentation!Someone in this thread hinted that there are also unannounced CPU cores in the SOC (in addition to the CPU tile)--but said so with no public evidence.
Figure it has to be 96 at the very least. Remember it's supposedly using N3. While dumb, it does mean that it would be a double shrink+ compared to where they are now.I think the GPU in these images is 64EU (maybe 32?). Not 100% sure though. But definitely not 192EU, at any rate.
Where do you see N3 for MTL? And I think it's just too small to be anything more than 64EU.Figure it has to be 96 at the very least. Remember it's supposedly using N3. While dumb, it does mean that it would be a double shrink+ compared to where they are now.
There's been some rumors that the IGP is N3 and not N5. Either way Alder Lake M is 96 EUs so you figure Intel wouldn't want to regress on that.Where do you see N3 for MTL? And I think it's just too small to be anything more than 64EU.