Discussion Intel current and future Lakes & Rapids thread

[Timmah!]

This is from Anandtech

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A Few Notes on Intel’s Knights Landing and MCDRAM Modes from SC15

www.anandtech.com

Interesting enough... Sapphire Rapids HMB will use the same HMB Modes used in Knights Landing

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I really don't understand why people believe that Intel made yet another expensive, non-modular monolithic CPU.

This quote is from Intel.

"At the heart of Sapphire Rapids is a tiled, modular SoC architecture that leverages Intel’s embedded multi-die interconnect bridge (EMIB) packaging technology to deliver significant scalability while maintaining the benefits of a monolithic CPU interface. Sapphire Rapids provides a single balanced unified memory access architecture, with every thread having full access to all resources on all tiles, including caches, memory and I/O. The result offers consistent low-latency and high cross-section bandwidth across the entire SoC."

Because for core counts lower than 30 one monolithic chip might be actually cheaper than those 2 tiles with EMIB and all the additional logic it requires and the complex substrate underneath.

If such chip truly exists, perhaps it will be that rumored "Alder Lake-X", rather than SPR. If the fact, that Intel was talking about tiled-based approach in regard to SPR is the issue here.

 

[Carfax83]

I believe you are being overoptimistic. Raptor Lake is an enhancement of Alder Lake, any IPC gains will be under 10%

I am certain there will be cases where the IPC gain is above 10%. IPC can vary a lot depending on workload and how it is being measured. At any rate, Raptor Lake is practically guaranteed to achieve double digit performance increases over Alder Lake in single thread performance through a combination of IPC, clock speed, cache upgrade, memory performance to varying degrees. As many more educated posters have stated, there is a lot of untapped potential still left in the core, in particular the memory subsystem, that can be exploited. The core itself is already very strong, but I think it is not being fed optimally in many cases. The increase in L2 cache should accelerate performance significantly. L2 cache is one area where Raptor Lake will be clearly ahead of Zen 4, with twice the cache!

 

[nicalandia]

Because for core counts lower than 30 one monolithic chip might be actually cheaper than those 2 tiles with EMIB and all the additional logic it requires and the complex substrate underneath.

This official roadmap for Workstations show them using Sapphire Rapids-SP(at least for the Experts, the rest will be still be based on Ice Lake)



There has been ES Samples of Sapphire Rapids having 20 cores. There is no Way Sapphire Rapids will stop being a Modular design, there is simply no enough volume to justify it.

 

[Timmah!]

This official roadmap for Workstations show them using Sapphire Rapids-SP(at least for the Experts, the rest will be still be based on Ice Lake)

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There has been ES Samples of Sapphire Rapids having 20 cores. There is no Way Sapphire Rapids will stop being a Modular design, there is simply no enough volume to justify it.

Thats roadmap for 2021. The product in question concerns Mainstream WS segment and Q3 2022, which is not shown in there.

 

[DrMrLordX]

The 24 Core SPR will be a MCM with 12 cores enabled on two tiles, the other two tiles will be dummy silicon for support.

Just an fyi, but you don't need to post the same image twice on the same page. You got the point across well enough.

As for a 24c Sapphire Rapids HEDT product, it sounds . . . interesting? It might wind up being slower than 16c Raphael, but if the platform options are good then AMD won't really have a competitor in that area (except for TR Pro which is vendor-exclusive atm and is limited to older Zen3 cores). Also gives Intel a place to dump tiles that they can't use as Sapphire Rapids, making it a win-win for them.

 

[Exist50]

nicalandia, I recommend not being so steadfastly against the idea of a monolithic SPR. I doubt it'll age well.

 

[IntelUser2000]

Yeah, makes sense for Xeon E without graphics.

Summary so far: Each 4x4 grid SPR tile has 15 cores, 32 Gen5 PCIe and 2 DDR5 memory channel support. SPR Xeon products:

1 tile: LGA1700 (Xeon E)
2 tiles or a bigger (e.g. 5x5) grid tile: HEDT socket (Xeon W)
4 tiles: LGA4677 (Xeon Scalable)

EMR will likely have support for 5x5 grid tiles. The size of the tiles and hence the number of cores is gated by the power consumption. Let’s see if by next year Intel 7 process will be further refined to address this.

There's one flaw in that analysis. With Alderlake, all you need is a compatible chipset for ECC support, which is a departure from previous generations.

Process doesn't have to be refined, as if the struggles with Sapphire Rapids are true, then the design and the core itself has lots of room for refinements. A good quality silicon can result in both lower power consumption and/or higher clock speeds, even if the process is exactly equal.

Thats exactly why i think its not that far-fetched idea, even though MLID is not exactly the most trusted source.
But then again, as a simple layman, i admit to have no real clue.

MLID has been nearly 100% accurate with Intel leaks. Don't know if he got any wrong which is why I say "nearly".

Yes we can't say they haven't made additional core configurations for Sapphire Rapids. That's very interesting. If they can get a 96 core version out with Emerald Rapids, it doesn't look as catastrophic, compared to previous rumors of being ending at 64 cores.

At 96 cores though, we might be seeing 4x 550mm2 tiles. Surely they don't seem to be taking advantage of tiles to reduce costs at all lol.

Problem with that is segmentation.
Be it monolithic or 2xchiplets then there's only 4 memory channels for the socket which is a marketing problem for bronze/silver xeons.

Not sure if that's necessarily a problem for a marketing point of view. It just gives them more flexibility. Before it was stuck with certain number of memory channels because of the way it's designed. Now you can segment them further. Kinda a wet dream for marketing.

You would think if they were capable of making a Larger compute tile with 24 cores that had quad channel memory, they would use it on the Top of the line Sapphire Rapids and charge $20,000 for it.

MLID(who has nearly perfect record with Intel leaks by the way) is talking about the 24-core 5GHz SPR part having anywhere between 200 to 300W TDP. One would think quadrupling that would cause issues. Can anyone guess where that might be?

 

[Exist50]

Wait, where's all this talk of 96 core EMR coming from? That's just not going to happen.

 

[ashFTW]

Process doesn't have to be refined, as if the struggles with Sapphire Rapids are true, then the design and the core itself has lots of room for refinements. A good quality silicon can result in both lower power consumption and/or higher clock speeds, even if the process is exactly equal.

Of course, lower power consumption can come from both process and design. I think there will be a bit of both. The EMIB bump pitch will shrink as well which will lead to more room on the chiplets, and the socket.

MLID(who has nearly perfect record with Intel leaks by the way) is talking about the 24-core 5GHz SPR part having anywhere between 200 to 300W TDP. One would think quadrupling that would cause issues. Can anyone guess where that might be?

Such a quad tile chip won’t be running such high clocks. a 5x5 grid tile will make a logical 10x10 grid, which will have increased latencies; don’t know if that’s going to be an issue. It could also be a 4x5 or 5x4 grid tile with 76 cores max. At the investor meeting in Feb, Pat in his keynote highlighted that EMR will have higher core counts.

 

[IntelUser2000]

Of course, lower power consumption can come from both process and design. I think there will be a bit of both.

Refinements have always existed in newer steppings and such but unless they announce such changes about process, then don't expect anything to be significant. The plusses for 14nm ranged from 3-5%.

The gains here will be practically zero. But SPR doesn't seem to be in a great condition, which gives room for improvement for Emerald Rapids. I can't imagine either of them good in any way, even with the currently reduced expectations. SPR has been seriously delayed, which isn't done to make it better, but is because likely they keep missing targets, and Emerald Rapids seems to be a fix of that.

Such a quad tile chip won’t be running such high clocks. a 5x5 grid tile will make a logical 10x10 grid, which will have increased latencies; don’t know if that’s going to be an issue.

A 60 core tile counts as being "increased core counts". That said 96 cores just because they might have a 24 core monolithic is a stretch. Yes it'll be clocked lower but at 4x the amount of cores, it'll be very power hungry. At 96 cores for a SPR package, each tile(and remember there's four of them) won't be far away from an entire Icelake-SP XCC die. 72 seems like a realistic upper limit for Emerald Rapids.

The best I can hope for is them shortening Emerald Rapids lifespan by continuing to sell them at low end(read: lower prices) so Granite Rapids can come faster. Ugh, cause otherwise, with a 12 month cycle, you end up with Emerald Rapids practically in 2024(Q3 2023?) and Granite Rapids practically in 2025(Q3 2024).

 

[jpiniero]

There's one flaw in that analysis. With Alderlake, all you need is a compatible chipset for ECC support, which is a departure from previous generations.

The mainstream line has always had an ECC option in the name of Xeon E3/E. There's a reason they didn't do Xeons for Alder Lake. That they would put a single tile SPR on LGA 1700 and call that Xeon E makes the most sense.

 

[IntelUser2000]

The mainstream line has always had an ECC option in the name of Xeon E3/E. There's a reason they didn't do that for Alder Lake for sure. That they would put a single tile SPR on LGA 1700 and call that Xeon E makes the most sense.

Yea that's not what MLID is saying. I assume similar thing might happen as it did with Kabylake-X, with mainstream being on a workstation socket since Alderlake-X rumor exists. So an "ultra low end" SPR socket with Alderlake core.

I don't know why they make certain SKUs like Kabylake-X. I figure they use such to test market reaction.

 

[DrMrLordX]

The best I can hope for is them shortening Emerald Rapids lifespan by continuing to sell them at low end(read: lower prices) so Granite Rapids can come faster.

Hopefully they'll shorten Sapphire Rapids' lifespan and get Emerald Rapids out quickly. Not sure if that's possible under the circumstances.

 

[jpiniero]

Yea that's not what MLID is saying.

Yeah but that's MLID. Intel obviously needs to do something with busted EMIB chiplets.

 

[IntelUser2000]

Yeah but that's MLID. Intel obviously needs to do something with busted EMIB chiplets.

And he has been nearly perfect with Intel leaks.
-Redwood Cove?
-Alderlake Hybrid?
-XeSS?
-Great Media encode/decode?

Hopefully they'll shorten Sapphire Rapids' lifespan and get Emerald Rapids out quickly. Not sure if that's possible under the circumstances.

The thing is, bringing out SPR fast as possible and shortening EMR is better, because the former brings out a plethora of new features, while the latter is a sad refresh.

 

[jpiniero]

The thing is, bringing out SPR fast as possible and shortening EMR is better, because the former brings out a plethora of new features, while the latter is a sad refresh.

The whole point of the sad refresh is to buy time. If the rumors are true and they are basically redoing Granite Rapids, you have to account for the time for that... not to mention what node would they fab the chiplets on (despite what Intel has said on the topic).

Icelake Server's real launch was in Q4, Sapphire is probably the same way, and Emerald comes a year later after that.

 

[DrMrLordX]

The thing is, bringing out SPR fast as possible and shortening EMR is better, because the former brings out a plethora of new features, while the latter is a sad refresh.

Something about Sapphire Rapids is broken. Cross your fingers and hope that they are at least able to ship some limited quantity now, and that they will get it shipping soon. Emerald Rapids, as sad as it may be, is little more than Sapphire Rapids with some improvements. Given how long Sapphire Rapids has been in development, it's entirely possible that Emerald Rapids may be close behind it, once Intel fixes the problems fundamental to tile-based server CPUs on 10ESF. It would really be better for Intel to mostly skip over Sapphire Rapids and move to the refresh product if possible.

 

[mikk]

And he has been nearly perfect with Intel leaks.
-Redwood Cove?
-Alderlake Hybrid?
-XeSS?
-Great Media encode/decode?

Much much more than this, MLID has real sources, this is not the question. He is quite accurate when it comes to Intel, even though not everything will be spot on even with real sources in the background. He said the desktop version of Meteor Lake is running since a couple of weeks, to me this is the best indication/source Meteor Lake for desktop is really coming.

 

[igor_kavinski]

He said the desktop version of Meteor Lake is running since a couple of weeks, to me this is the best indication/source Meteor Lake for desktop is really coming.

No one should be surprised. Intel has learnt enough harsh lessons by now to keep plan Bs at the ready. I wouldn't be surprised if they have multiple contingencies in place to cover their collective bottoms.

 

[gdansk]

The mainstream line has always had an ECC option in the name of Xeon E3/E. There's a reason they didn't do Xeons for Alder Lake. That they would put a single tile SPR on LGA 1700 and call that Xeon E makes the most sense.

Just to be clear: the non-Xeon Alder Lake chips support ECC in W680 boards now. Why would they even need a LGA1700 Xeon anymore? Is a single SPR tile going to be that much more capable?

 

[jpiniero]

Just to be clear: the non-Xeon Alder Lake chips support ECC in W680 boards now. Why would they even need a LGA1700 Xeon anymore? Is a single SPR tile going to be that much more capable?

It'd avoid the issues with the small cores for low end servers. AVX-512, AMX, etc. Not to mention they are going to have a ton of busted EMIB chiplets so they got to do something with those.

 

[IntelUser2000]

Just to be clear: the non-Xeon Alder Lake chips support ECC in W680 boards now. Why would they even need a LGA1700 Xeon anymore? Is a single SPR tile going to be that much more capable?

Actually yes if they are really getting a 24-core monolithic chip ready.

But that's not the issue. The thing is it's never done that way. The opposite way was done, which in this case is bringing Alderlake to LGA4677 socket as they did with Kabylake-X.

Because more pin count means more room for power delivery and memory channels, so they need to do more work to get Sapphire Rapids tile compatible with LGA1700 than other way around.

Something about Sapphire Rapids is broken. Cross your fingers and hope that they are at least able to ship some limited quantity now, and that they will get it shipping soon.

Guess the final result is the same either way. If Sapphire Rapids is delayed than something is out of their control and shortening SPR's lifespan makes sense over reducing EMR's lifespan.

So the possibility is that SPR might look like Cooper Lake, where it launched only with mid-range chips right from the get go and it only makes sense from a market's perspective. And later on EMR can come with only higher end variants later on, and replace both with Granite Rapids.

 

[DrMrLordX]

So the possibility is that SPR might look like Cooper Lake, where it launched only with mid-range chips right from the get go and it only makes sense from a market's perspective. And later on EMR can come with only higher end variants later on, and replace both with Granite Rapids.

Yeah that seems like a safe bet.

 

[Redfire]

The mainstream line has always had an ECC option in the name of Xeon E3/E. There's a reason they didn't do Xeons for Alder Lake. That they would put a single tile SPR on LGA 1700 and call that Xeon E makes the most sense.

Xeon-E is only launched for every other consumer generation. They didn't do one for Alder Lake because they launched one for Rocket Lake already.
CFL-R : Mehlow (Xeon E-22XX)
RKL-S : Tatlow (Xeon E-23XX)
RPL-S : Catlow (Xeon E-24XX?)

Just to be clear: the non-Xeon Alder Lake chips support ECC in W680 boards now. Why would they even need a LGA1700 Xeon anymore? Is a single SPR tile going to be that much more capable?

Support for ECC in regular Alder Lake chips replaces what was previously the Xeon W-1000 series, not the Xeon-E series. I'm not actually sure what the difference between the two is, but they're two separate product lines.

Something about Sapphire Rapids is broken. Cross your fingers and hope that they are at least able to ship some limited quantity now, and that they will get it shipping soon. Emerald Rapids, as sad as it may be, is little more than Sapphire Rapids with some improvements. Given how long Sapphire Rapids has been in development, it's entirely possible that Emerald Rapids may be close behind it, once Intel fixes the problems fundamental to tile-based server CPUs on 10ESF. It would really be better for Intel to mostly skip over Sapphire Rapids and move to the refresh product if possible.

Sapphire Rapids hasn't had an "excessive" amount of issues on a chip-level as far as I'm aware. Most of the issues have been related to the platform and validation. I don't believe it's a "fundemental" problem with tile-based CPUs on Intel 7. Emerald Rapids is coming out at earliest, in Q1-2023, quite a bit after Sapphire Rapids.

 

[jpiniero]

Xeon-E is only launched for every other consumer generation. They didn't do one for Alder Lake because they launched one for Rocket Lake already.
CFL-R : Mehlow (Xeon E-22XX)
RKL-S : Tatlow (Xeon E-23XX)
RPL-S : Catlow (Xeon E-24XX?)

No, they just didn't do one for Comet Lake, only Xeon W. Every gen previous to that has had one (which goes back to Xeon E3).