Discussion Intel current and future Lakes & Rapids thread

[nicalandia]

Here is a 8 + 8 Meteor Lake mock up compared to 8 + 8 Alder Lake, they look identical as far as core placement, core shape and ring bus


Meteor Lake




Alder lake

 

[dullard]

That was in an Intel presentation!

Do you recall which one? I don't remember seeing that anywhere. Thanks.

 

[dullard]

I'm sort of crazy.

View attachment 61370

My interpretation based on all the rumors being bombarded all over.

CPU tile should be the smallest: https://videocardz.com/newz/first-die-shot-of-intel-14th-gen-core-meteor-lake-processor-emerges

That CPU photo and the Videocardz die shot are either not the same 2+8 CPU or you have them mislabeled. The aspect ratio doesn't work out the way you labelled it.

 

[Timmah!]

Here is a 8 + 8 Meteor Lake mock up compared to 8 + 8 Alder Lake, they look identical as far as core placement, core shape and ring bus


Meteor Lake

View attachment 61376


Alder lake

View attachment 61375

I presume this would be the right time for the obligate "Corporate needs you to find differences..."

 

[nicalandia]

Do you recall which one? I don't remember seeing that anywhere. Thanks.

Perhaps he is referring to this?



The External N3 is a compute tile built by TSMC,

 

[Exist50]

Do you recall which one? I don't remember seeing that anywhere. Thanks.

Slide 215.

https://newsroom.intel.com/wp-content/uploads/sites/11/2020/08/Intel-Architecture-Day-2020-Presentation-Slides.pdf

 

[dullard]

Slide 215.

https://newsroom.intel.com/wp-content/uploads/sites/11/2020/08/Intel-Architecture-Day-2020-Presentation-Slides.pdf

Thank you for the link. But that is in Intel's long term plans, it doesn't specifically state it is in Meteor Lake. Is there any evidence that it is in Meteor Lake?

For example, on slide 214 there are Media tiles that you have previously stated are NOT in Meteor Lake.

 

[nicalandia]

That CPU photo and the Videocardz die shot are either not the same 2+8 CPU or you have them mislabeled.

Clearly Mislabeled, the CPU Compute is on the Top left corner, the CPU Tile is clearly capable of 8+8

Looks like PC-Watch got some photos of Intel's upcoming products:

And Nowhere to be found the "Mythical" Monolithic HEDT Sapphire Rapids-X?

 

[jpiniero]

And Nowhere to be found the "Mythical" Monolithic HEDT Sapphire Rapids-X?

In fairness, Intel hasn't mentioned Sapphire Rapids-X yet.

 

[Timmah!]

And Nowhere to be found the "Mythical" Monolithic HEDT Sapphire Rapids-X?

Neither is Raptor Lake and that one is comíng for sure, right?

 

[nicalandia]

Neither is Raptor Lake and that one is coming for sure, right?

True.

 

[ashFTW]

MTL: Everyone is only talking about the 4 top tiles. There is also a base Foveros tile, and it will minimally contain the interconnect (ring I assume) to connect all the top tiles. But there is an opportunity for a system level cache as well. And it may be made on 22nm just like Lakefield, though that doesn’t lend itself to high capacity SRAM.

 

[jpiniero]

MTL: Everyone is only talking about the 4 top tiles. There is also a base Foveros tile, and it will minimally contain the interconnect (ring I assume) to connect all the top tiles. But there is an opportunity for a system level cache as well. And it may be made on 22nm just like Lakefield, though that doesn’t lend itself to high capacity SRAM.

Doesn't sound like it. All I've seen is that the base Foveros is passive. And it's on 10 nm. As to why I have no clue.

 

[ashFTW]

Doesn't sound like it. All I've seen is that the base Foveros is passive. And it's on 10 nm. As to why I have no clue.

And how are the top tiles connected, if not through the base tile? Note that there is no EMIB here, like in SPR.

 

[jpiniero]

And how are the top tiles connected, if not through the base tile?

I would assume they are being connected through the base tile. But the base tile is not doing anything other than very basic dumb routing.

 

[ashFTW]

So the MTL base die is just a passive interposer? Nothing “Foveros” about it then!

Are SPR EMIB die also passive?

By the way, I found an interesting paper that discusses the cost and performance trade offs of active and passive interposers, which should apply to Intel EMIB and Foveros technologies as well.

https://web.ece.ucsb.edu/~iakgun/files/SLIP2019.pdf

 

[IntelUser2000]

Do you recall which one? I don't remember seeing that anywhere. Thanks.

In addition to Exist50's I also gave you this link in response to you asking.

Page 618 - Discussion - Intel current and future Lakes & Rapids thread

Page 618 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

Go back to that post and few posts above that.

For example, on slide 214 there are Media tiles that you have previously stated are NOT in Meteor Lake.

That doesn't mean it has to be in Meteorlake, it's only their first approach. It says "Long Term Vision" right below it.

So the MTL base die is just a passive interposer? Nothing “Foveros” about it then!

Are SPR EMIB die also passive?

Well there are rather nice advantages of Foveros over using EMIB or even using a conventional organic interposer.

EMIB requires extra little chips, and uses more power. Organic interposers are the cheapest but only transfers limited amount of data and also not very power efficient because of distance limitation. They are talking micron width distances with EMIB/Foveros. Yes for things like PCIe 4 x16, that's fine. But you want 500GB/s+ bandwidth then interconnects start eating a lot of power.

With Foveros you can emulate being on-die interconnect power-wise and performance wise. Intel's big problem has been not having an on-die PCH, and Foveros can potentially solve this issue. Meteorlake is the generation where I can see big battery life gains and significantly close the gap with competitiors like AMD, and even ARM!

Having a fab in-house plus an irrational focus on margins and the bottom line is why they stuck to the off-die memory controller for so long, and why they didn't move the PCH on-die. It used to be split into the CPU, GMCH, and the ICH. The GMCH moved into the CPU, but didn't happen until Nehalem in 2010 because it meant their fabs would be under utilized.

If you move the PCH on-die, you can't have a chipset to fill up the N-1 fab anymore. So delay as long as possible. EMIB, Foveros, tiles potentially solve this problem. That's why Pat bought Tower semi, because it brings expertise that doesn't exist in Intel, and allows utilization of older fabs.

Also on a client product, especially desktops, there are thermal issues to be solved, because while SRAM is pretty cool, logic is not. That'll impact not only reliability but performance as well. There are cost issues too. Just connecting the tiles is all it needs to do. Otherwise you likely need redesign with the ring and everything.

Sapphire Rapids EMIB is probably not passive though. I think EMIB in this case is to get low interconnect latency and high bandwidth between the tiles, because the applications Enterprise customers use are very sensitive to that. The Xeon MPs of long ago and Xeon E7s all had some fancy techniques probably just to fit that crowd. Yea I'm not sure if passive/active applies for EMIB.

 

[deasd]

wrong thread, sry

 

[witeken]

Meteor Lake bottom die being just a passive interposer? I don't even.

Meteor Lake is Lakefield 2.0. The bottom die is the PCH, which per tradition is built on the N-1 node, in this case 10nm Foveros.

Proof: see the high density package and tell me where the PCH is... https://wccftech.com/intel-shows-off-14th-gen-meteor-lake-standard-high-density-die-packages-cpu-tiles-produced-by-intel-gpu-tiles-by-tsmc/

This is my first post in years just to correct this nonsensical "theory". Foveros is active interposer.

Edit: if Intel just needed passive connections it would use EMIB, which is Intel's ultra-low cost alternative to passive interposer. @jpiniero @IntelUser2000 @ashFTW

 

[jpiniero]

Proof: see the high density package and tell me where the PCH is... https://wccftech.com/intel-shows-off-14th-gen-meteor-lake-standard-high-density-die-packages-cpu-tiles-produced-by-intel-gpu-tiles-by-tsmc/

The SoC.

 

[Anhiel]

If my estimation on the die size is roughly correct the total area (with empty space) is around 178 mm^2.
So the top left should be Intel4 8c+16c compute part. The tile below would be N4 IO.
The center part would be N3 iGPU but it has space for 384 EU so it either is:
2 media engine + 384 EU
or
2 media engine + 192 EU + 6 tensor processing core (TPC) or similar
The right lean tile would be N5 SOC.

 

[Exist50]

In addition to Exist50's I also gave you this link in response to you asking.

Page 618 - Discussion - Intel current and future Lakes & Rapids thread

Page 618 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

Go back to that post and few posts above that.

Good catch. @dullard, if you look very closely at the diagram on Slide 8, it includes "Atom Complex". No harm in treating it as a rumor till it's confirmed, but do know that it does exist.

Clearly Mislabeled, the CPU Compute is on the Top left corner, the CPU Tile is clearly capable of 8+8

I'm certain this is a 2+8 compute die. Way too small to be 6+8, much less 8+8.

With Foveros you can emulate being on-die interconnect power-wise and performance wise.

You need hybrid bonding to get close to monolithic. Foveros has a smaller bump pitch than EMIB, which is probably why it's used here, but it's still not quite monolithic.

Meteorlake is the generation where I can see big battery life gains and significantly close the gap with competitiors like AMD, and even ARM!

Unfortunately, I think you'll be disappointed, but I hope my pessimism ends up being incorrect.

Meteor Lake is Lakefield 2.0. The bottom die is the PCH, which per tradition is built on the N-1 node, in this case 10nm Foveros.

witeken, if you're going to make such a big deal out of it, it would help to actually be correct... The base die on MTL is passive. No cache nor PCH.

 

[dullard]

Good catch. @dullard, if you look very closely at the diagram on Slide 8, it includes "Atom Complex". No harm in treating it as a rumor till it's confirmed, but do know that it does exist.

Note: I am not going to deny that cores in the big tile exist. I hope they do, since the more technology and the more cores out there the better off we are will be. But, even that link doesn't specify Meteor Lake. We can imply that it is in Meteor Lake due to the same 3-tile graphic used for other Meteor Lake presentations (ignoring the obvious simplification that Meteor Lake isn't 3 tiles). But that is also the same image used for Arrow Lake. So, these are still just hints at this point for those of us without inside information.

 

[nicalandia]

I'm certain this is a 2+8 compute die. Way too small to be 6+8, much less 8+8.

Is this better?

 

[Exist50]

Note: I am not going to deny that cores in the big tile exist. I hope they do, since the more technology and the more cores out there the better off we are will be. But, even that link doesn't specify Meteor Lake. We can imply that it is in Meteor Lake due to the same 3-tile graphic used for other Meteor Lake presentations (ignoring the obvious simplification that Meteor Lake isn't 3 tiles). But that is also the same image used for Arrow Lake. So, these are still just hints at this point for those of us without inside information.

Well Arrow Lake is supposed to use the same SoC tile as Meteor Lake, right? So...

Is this better?

View attachment 61429

Purely in terms of the CPU tile, yeah, that looks right.