Do you recall which one? I don't remember seeing that anywhere. Thanks.
In addition to Exist50's I also gave you this link in response to you asking.
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forums.anandtech.com
Go back to that post and few posts above that.
For example, on slide 214 there are Media tiles that you have previously stated are NOT in Meteor Lake.
That doesn't mean it has to be in Meteorlake, it's only their first approach. It says "Long Term Vision" right below it.
So the MTL base die is just a passive interposer? Nothing “Foveros” about it then!
Are SPR EMIB die also passive?
Well there are rather nice advantages of Foveros over using EMIB or even using a conventional organic interposer.
EMIB requires extra little chips, and uses more power. Organic interposers are the cheapest but only transfers limited amount of data and also not very power efficient because of distance limitation. They are talking micron width distances with EMIB/Foveros. Yes for things like PCIe 4 x16, that's fine. But you want 500GB/s+ bandwidth then interconnects start eating a lot of power.
With Foveros you can emulate being on-die interconnect power-wise and performance wise. Intel's big problem has been not having an on-die PCH, and Foveros can potentially solve this issue. Meteorlake is the generation where I can see big battery life gains and significantly close the gap with competitiors like AMD, and even ARM!
Having a fab in-house plus an irrational focus on margins and the bottom line is why they stuck to the off-die memory controller for so long, and why they didn't move the PCH on-die. It used to be split into the CPU, GMCH, and the ICH. The GMCH moved into the CPU, but didn't happen until Nehalem in 2010 because it meant their fabs would be under utilized.
If you move the PCH on-die, you can't have a chipset to fill up the N-1 fab anymore. So delay as long as possible. EMIB, Foveros, tiles potentially solve this problem. That's why Pat bought Tower semi, because it brings expertise that doesn't exist in Intel, and allows utilization of older fabs.
Also on a client product, especially desktops, there are thermal issues to be solved, because while SRAM is pretty cool, logic is not. That'll impact not only reliability but performance as well. There are cost issues too. Just connecting the tiles is all it needs to do. Otherwise you likely need redesign with the ring and everything.
Sapphire Rapids EMIB is probably not passive though. I think EMIB in this case is to get low interconnect latency and high bandwidth between the tiles, because the applications Enterprise customers use are very sensitive to that. The Xeon MPs of long ago and Xeon E7s all had some fancy techniques probably just to fit that crowd. Yea I'm not sure if passive/active applies for EMIB.