Question Zen 6 Speculation Thread

[marees]

Which really makes me wonder what's the point of Gorgon Point. If we are ~9 months away from launch of Zen6 mobile SKUs, what's the point of launching any more Zen 5 mobile SKUs in this short time window, when these Gorgon Point SKUs will overlap substantially with Zen 6.

It would make more sense if Gorgon Point was Zen 6 with RDNA3.5 and Medusa Zen 6 with RDNA5

So zen 6 mobile apus (Medusa point/premium/halo) are 2027+

 

[StefanR5R]

They update the Venice performance indication:

View attachment 133690

the old one:

View attachment 133691


from '1.7x Gen vs Gen Performance' to ' '>1.7x Performance & Efficiency', that's a very big difference and change the speculation quite a bit.

For completeness, this is the end note which was provided with the >1.7x claim:

VEN-001A: SPECrate®2017_int_base comparison based on AMD internal estimates for top of stack 2P 6th Gen EPYC CPU and 5th Gen EPYC measurements as of 10/30/2025. Preliminary performance estimates based on AMD engineering projections or measurements as of 10/30/2025 and subject to change.

(from Dan McNamara's segment at FAD 2025)

 

[regen1]

Though AFAIK there has been no formal announcement my understanding is that like N2P, A14 will also be offered in both flavors.

There was official info regarding A14 versions in TSMC Tech Symposium 2025.
A14 targeted for 2028 and A14 with BSPDN(Super Power Rail) planned for 2029.

2025 Symposium Highlights - Taiwan Semiconductor Manufacturing Company Limited

Market Outlook Dr.

www.tsmc.com

 

[Josh128]

I wouldn't think much of it. Who expects 70% better gen on gen performance?

Well, it says "greater than" when it used to not. I think, taking this at face value, depending on the power levels chosen, this means it can be either or, and the "greater than" sign indicates 70% is the minimum floor to expect.

 

[adroc_thurston]

Well, it says "greater than" when it used to not. I think, taking this at face value, depending on the power levels chosen, this means it can be either or, and the "greater than" sign indicates 70% is the minimum floor to expect.

You'll get like 1.8x sir2017 skt perf bump at 20% more power.
It's very good.

 

[Elfear]

For completeness, this is the end note which was provided with the >1.7x claim:

(from Dan McNamara's segment at FAD 2025)

Hmm. This is probably a dumb question but could part of the >1.7x increase come from a faster interconnect between the two CPUs (2P)? If so, wouldn't that indicate that the actual IPC increase we'll see for desktop may be lower than expected? Just trying to calibrate my expectations.

 

[Geddagod]

Hmm. This is probably a dumb question but could part of the >1.7x increase come from a faster interconnect between the two CPUs (2P)? If so, wouldn't that indicate that the actual IPC increase we'll see for desktop may be lower than expected? Just trying to calibrate my expectations.

IIRC scaling is already pretty much linear on current systems.

 

[StefanR5R]

Hmm. This is probably a dumb question but could part of the >1.7x increase come from a faster interconnect between the two CPUs (2P)? If so, wouldn't that indicate that the actual IPC increase we'll see for desktop may be lower than expected? Just trying to calibrate my expectations.

The less prominent SPECspeed benchmark suite works like this: One instance of a benchmarking program is run, and the user selects up to how many software threads the program is to use.

But the SPECrate benchmark suite in question works the other way around: Any instance of the benchmarking program is single-threaded, and the user selects how many instances are to run at once. (What AMD didn't spell out but most certainly did is that they ran as many instances as there are hardware threads in the respective computer. Or, in case of Venice, extrapolated from their current samples how such an all-threads run will turn out in the final product.)

The simultaneously running copies of SPECrate suite programs do not communicate with each other. This is different to supercomputing in which communications between subtasks is a major factor. Thus, in a SPECrate run, there is a tiny amount of cross-socket communication performed by the benchmark launcher framework, but this is really negligible.

Some more info: https://www.spec.org/cpu2017/Docs/overview.html

 

[StefanR5R]

PS, about...

...the actual IPC increase we'll see for desktop...

First, the figure is for SPECrate 2017 Integer¹ — that's different from, say, Cinebench R23 which is scalar FP² with light use of the memory subsystem, and even more different from average frames per seconds in video games. :-)

Second, it is for absolute computer performance at unknown core clock frequencies. What we more or less know is that it's 2x Turin-dense top SKU (3nm, 192 cores/socket, 500 W/socket) versus 2x Venice-dense top SKU (2nm, 256 cores/socket, 600 W/socket). Many have tried to derive "IPC" uplift from such whole-computer performance uplift figures before, but as we know all too well, there really is quite a bit of guesswork involved in such attempts.

________
¹) SPECrate 2017 Integer actually does have three game subtests in it: Chess, Go, and Sudoku. :-) Of course SPEC does not call them g4m1ng subtests, but, and I am not kidding, AI subtests. Furthermore there are Perl interpreter, C compiler, route planning, LAN/WAN simulator, XSLT converter, x264 video compressor, and xz data compressor subtests.

edit:
²) or more correctly, "a mix of scalar SSE and 256-bit AVX".

 

[Josh128]

 

[adroc_thurston]

View attachment 133793

Hey it also has AMD-V updates.

 

[StefanR5R]

View attachment 133793

If "the actual IPC increase we'll see for desktop" was to be derived from this one, quite a bit of guesswork would be involved too, but for different reasons.

 

[Elfear]

The less prominent SPECspeed benchmark suite works like this: One instance of a benchmarking program is run, and the user selects up to how many software threads the program is to use.

But the SPECrate benchmark suite in question works the other way around: Any instance of the benchmarking program is single-threaded, and the user selects how many instances are to run at once. (What AMD didn't spell out but most certainly did is that they ran as many instances as there are hardware threads in the respective computer. Or, in case of Venice, extrapolated from their current samples how such an all-threads run will turn out in the final product.)

The simultaneously running copies of SPECrate suite programs do not communicate with each other. This is different to supercomputing in which communications between subtasks is a major factor. Thus, in a SPECrate run, there is a tiny amount of cross-socket communication performed by the benchmark launcher framework, but this is really negligible.

Some more info: https://www.spec.org/cpu2017/Docs/overview.html

Thanks for the detailed explanation.

 

[MS_AT]

or more correctly, "a mix of scalar SSE and 256-bit AVX".

To be even more correct, it's 128b AVX https://chipsandcheese.com/p/cinebench-2024-reviewing-the-benchmark?utm_source=publication-search when you look at the top 43 used instructions. If they were 256b they would use YMM instead of XMM in the name.

 

[Chicken76]

I haven't seen yet a consensus about how the 12-core die has the cores arranged and interconnected. Is it a 4x3 grid or 6x2?
Are they going to disable cores in triplets or pairs?

 

[DrMrLordX]

I wouldn't think much of it. Who expects 70% better gen on gen performance?

I expect 68% . . .

A14 targeted for 2028 and A14 with BSPDN(Super Power Rail) planned for 2029.

Huh. So if there are Zen7 variants that don't use BSPDN, then 2028 Zen7 is a possibility.

 

[511]

Huh. So if there are Zen7 variants that don't use BSPDN, then 2028 Zen7 is a possibility.

It will be H2 28 most likely if true

 

[luro]

Guys, the cadence is always 4Q’s.

 

[yuri69]

So zen 6 mobile apus (Medusa point/premium/halo) are 2027+

CES 2027 has been the plan for the initial wave of Medusa. Niche stuff like Halo comes later in 2027 (if not canned).

CES 2026 should see Gorgon aka new revision of Strix with an overlocked NPU.

 

[Josh128]

I haven't seen yet a consensus about how the 12-core die has the cores arranged and interconnected. Is it a 4x3 grid or 6x2?
Are they going to disable cores in triplets or pairs?

6x2 (12C CCX) with shared L3, just like Zen 5c is 8x2 (16C CCX) with shared L3.

 

[StefanR5R]

To be even more correct, it's 128b AVX https://chipsandcheese.com/p/cinebench-2024-reviewing-the-benchmark?utm_source=publication-search when you look at the top 43 used instructions. If they were 256b they would use YMM instead of XMM in the name.

On a quick look they don't have the same breakdown for CB R23, but it's reasonable to assume that this is not more advanced than CB 2024 WRT modern ISA uses.

 

[511]

On a quick look they don't have the same breakdown for CB R23, but it's reasonable to assume that this is not more advanced than CB 2024 WRT modern ISA uses.

> Modern ISA
> Looks Inside still stuck at AVX2 Baseline
also

x86 Benchmark 10% of the instructions are mov and lea 🤣

 

[poke01]

You know we can use Blender….

Supports AVX512 and isn’t coddled up with Intel conspiracy

 

[adroc_thurston]

You know we can use Blender….

Supports AVX512 and isn’t coddled up with Intel conspiracy

It's a GPU benchmark.
Just use sir2017.

 

[poke01]

It's a GPU benchmark.
Just use sir2017.

It’s a good cou benchmark too for nT better than cinememe