LightningZ71
Platinum Member
- Mar 10, 2017
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Whatever LP is implemented with, it must be logically capable of supporting every instruction that the other cores can. They can go even further with densifying the cores at the expense of clocks, and with lower target speeds, spend fewer XTORS on critical paths. Depending on the instruction, they can even move to just supporting some things in microcode. It just must be feature complete.

