Question Zen 6 Speculation Thread

[adroc_thurston]

I thought N3C for the poors.

The selling point is the 1-1 fin pop option but that's like not usable for AMD.

 

[Tangopiper]

I have been assuming for a while now there will be another iteration of N2, call it "N2PP" for now, that they introduce in H2 2027 to fill the gap between N2P and A14, because I can't see them going two years without even a small improvement. If you want product to reach customer hands in 2028 that's what you're going to use, not A14.

N2X and A16 fill that role I would say. Little earlier that 2H27 but still ‘late’ in N2 family life cycle.

Not like TSMC has any competition to speak of anyway, so they are hardly under pressure to introduce stop gaps to keep customers at the door…

 

[adroc_thurston]

Not like TSMC has any competition to speak of anyway, so they are hardly under pressure to introduce stop gaps to keep customers at the door…

SF2 derivatives are very much candidates.

 

[Geddagod]

N2X and A16 fill that role I would say. Little earlier that 2H27 but still ‘late’ in N2 family life cycle.

Not like TSMC has any competition to speak of anyway, so they are hardly under pressure to introduce stop gaps to keep customers at the door…

The situation with the X nodes is honestly baffling. Not one company is willing to admit to using an X node, even AMD who according to techinsights supposedly do use N4X, which AMD insists is N4P.
Do we know any products that are officially listed as N4X, or will be N3X?

 

[adroc_thurston]

or will be N3X?

Glymur is N3X.

 

[Tangopiper]

SF2 derivatives are very much candidates.

Samsung Foundry actually yielding something? With a PDK that is useable? I’ll believe it when I see it, forgive my skepticism 😂

Pretty sure SF2 is just a rebrand of SF3P as well? Not that these numbers are anything but marketing, I grant you.

 

[Tangopiper]

The situation with the X nodes is honestly baffling. Not one company is willing to admit to using an X node, even AMD who according to techinsights supposedly do use N4X, which AMD insists is N4P.
Do we know any products that are officially listed as N4X, or will be N3X?

Large customers like AMD and Apple don’t really use the advertised nodes per se. They use whatever variation DTCO cooks up.

So AMD may well be technically correct when they say N4P, as that was the basis for their DTCO N4 variant.

 

[adroc_thurston]

Pretty sure SF2 is just a rebrand of SF3P as well?

Naa.

 

[inquiss]

View attachment 133631
Zen6 is on N3-ACK

Yeah but what is the reasoning? Can't just be true unless there is a reason.

 

[Tangopiper]

Naa.

From an Anandtech article 13th June 2024:
"We have refined and improved the SF3P, resulting in what we now refer to as SF2," a Samsung spokesperson told AnandTech. "This enhanced node incorporates various process design improvements, delivering notable power, performance, and area (PPA) benefits."

Samsung Foundry Unveils Updated Roadmap: BSPDN and 2nm Evolution Through 2027

web.archive.org

Tom’s article also included

Samsung's new roadmap unveils its 2nm process nodes and outlines backside power delivery plans

Samsung renames SF3P to SF2 due to better performance, power, and density.

www.tomshardware.com

Granted they claim various improvements. Not sure that’ll be enough to fight N2.

 

[Geddagod]

Glymur is N3X.

All I've seen abt that is this... confusing... tweet, no idea what to make of it

Granted they claim various improvements. Not sure that’ll be enough to fight N2.

Looks like its gonna be worse than N3P

 

[Thunder 57]

Yeah.
One only needs to focus on the 4 key buzzwords they used for Zen6 and Zen7:
"AI - AI - Matrix - AI"

Nobody but investors cares about that, while investors don't care about anything else atm.

Looking forward to a GN video with a segment on this making fun of it with an "AIAIAIAIAI" segment. As well they should.

 

[OneEng2]

But what would be beneficial to the signal-to-noise ratio of this thread is that you realize that the reasoning for which you asked is already there, and there is nothing more beyond this.

Whatever. If people can't give any evidence, or any reasoning, I'll just keep ignoring their assertions ..... if that's OK with you.

You don't need to agree with me, or require any reasoned responses if you wish.

I do think Zen 7 is gonna be 2028 though. 2 year cadence.

I actually think it's more likely that Zen 7 will be later than that.

A16 Has BSPDN the PPA improvement is from that alone and if Zen 7 is truly A14 it's H2 28 launch at best

I am guessing even later.

But zen 7 only in 2029 for cient (desktop & laptop). The epyc, especially dense versions, could be rushed out in 2028 though.

More likely. I agree.

I have been assuming for a while now there will be another iteration of N2, call it "N2PP" for now, that they introduce in H2 2027 to fill the gap between N2P and A14, because I can't see them going two years without even a small improvement. If you want product to reach customer hands in 2028 that's what you're going to use, not A14.

I have a feeling that we need to all get our loving out on Zen 6 because it's likely to be a long cold wait for Zen 7.

IIRC, A16 will be N2 + BSPDN using the same libraries. Will A14 be offered in both flavors as well? I have started to have some serious respect for TSMC in bringing well hardened processes to the market. Note: N3B was a good node, but jumped the shark in terms of cost and wafer process complexity (and time). It needed a refinement and a rethink to end up at the N3E that was much more popular ...... so I am wondering about A16 maybe being the N3B of this generation?

If so, perhaps A14 will be a really nice node for TSMC.

 

[511]

The issue is A16 -> A14 is like 10% PPA improvement

 

[Philste]

All I've seen abt that is this... confusing... tweet, no idea what to make of it

"All the products we announced yesterday are built predominately in N3P, but we have made opportunistic choices using N3X transistors to get benefit of higher speeds wherever applicable."

With FinFlex, you can pretty much do what you want. You can build 16 Cores with N3P and 2 Cores with N3X in one monolithic Die, which Qualcomm did.

 

[deasd]

They update the Venice performance indication:



the old one:




from '1.7x Gen vs Gen Performance' to ' '>1.7x Performance & Efficiency', that's a very big difference and change the speculation quite a bit.

 

[Thunder 57]

They update the Venice performance indication:

View attachment 133690

the old one:

View attachment 133691


from '1.7x Gen vs Gen Performance' to ' '>1.7x Performance & Efficiency', that's a very big difference and change the speculation quite a bit.

I wouldn't think much of it. Who expects 70% better gen on gen performance?

 

[Doug S]

IIRC, A16 will be N2 + BSPDN using the same libraries. Will A14 be offered in both flavors as well?

Though AFAIK there has been no formal announcement my understanding is that like N2P, A14 will also be offered in both flavors. Until the downsides of BSPDN are remediated, or the node progression either increases the upside for using it or begins to institute a penalty for not using it, it seems they'll have to maintain two tracks.

 

[adroc_thurston]

Who expects 70% better gen on gen performance?

Me.

 

[Thibsie]

I wouldn't think much of it. Who expects 70% better gen on gen performance?

It's for the whole cpu taking account of mre cores.

 

[Bigos]

256/192 cores is 1.(3) more cores. 1.7 / 1.(3) = 1.275. So at least 27.5% higher perf per core (which can come from plethora of factors, perf per clock is one of them).

This was already known, the new thing is the ">" sign.

 

[adroc_thurston]

256/192 cores is 1.(3) more cores. 1.7 / 1.(3) = 1.275. So at least 27.5% higher perf per core (which can come from plethora of factors, perf per clock is one of them).

This was already known, the new thing is the ">" sign.

Yeah they'll hit like 1.8x socket perf there.
Pretty good.

 

[511]

1.7-1.8X is reasonable with 1.33X Cores 2.5 Mem Bandwidth 1 node and 1 arch improvement it would be bad if we are. Not getting this.

 

[ETI4711]

"All the products we announced yesterday are built predominately in N3P, but we have made opportunistic choices using N3X transistors to get benefit of higher speeds wherever applicable."

With FinFlex, you can pretty much do what you want. You can build 16 Cores with N3P and 2 Cores with N3X in one monolithic Die, which Qualcomm did.

That's what Qualcomm says. But it doesn't match what TSMC says about N3P and N3X.

TSMC has never cared what customers say about which processes they use.

 

[Tuna-Fish]

256/192 cores is 1.(3) more cores. 1.7 / 1.(3) = 1.275. So at least 27.5% higher perf per core (which can come from plethora of factors, perf per clock is one of them).

I expect the nT clocks to go up substantially, the much better node helps that even more than 1T.