Question Zen 6 Speculation Thread

[StefanR5R]

The only Venice that Lisa mentioned officially was "up to" 256 core dense version, period, which is definitely the 2nm version. That doesnt negate the possibility that non-dense versions might not be using 2nm, unless someone has something more than what I saw, which is this:

View attachment 133355

Not only does this say "up to 256 cores", it also says "2nm · Zen 6". Not "down to 2nm · Zen 6". There is no mention of a 3nm variant of Venice anywhere, neither in the "Advancing AI 2025" presentation on June 12, nor in the Q3/2025 Financial Report and associated Q&A.

So if a 3nm Venice is not mentioned, the only remaining possible explanation is that AMD cancelled the 3nm CCD project and backported it to Global Foundries 12nm instead. :-P

 

[Joe NYC]

This is great news, the fact that we may be SOME news. Until then I suppose I'll just have to endure more scolding from Mr. Teenage Angst Thurston lecturing me about Liberace and stuff.

🙂

BTW, owning the libs is not related to Liberace.

 

[vanplayer]

It's still possible that Zen6 OlympicRange would be based on N3P, still remain to be seen and I could be wrong. The reason behind is complicated....But don't worry, I don't think the performance projection VS Novalake would be changed that much even AMD still use inferior process on future CPU. Also Medusa lineup is another story.

50/50 for either N2 or N3 on OlpR.

 

[gdansk]

But don't worry, I don't think the performance projection VS Novalake would be changed that much

That doesn't make sense to me. I think a 24 core deficit and a worse process would be too much to overcome.

 

[adroc_thurston]

50/50 for either N2 or N3 on OlpR.

There is no '50/50'.
Most things Zen6 taped out a while ago.

 

[Hulk]

🙂

BTW, owning the libs is not related to Liberace.

 

[OneEng2]

If someone here posted something like that and refused to even categorize HOW he claims to know it I'd give it the zero credibility it deserves.

Seems reasonable. Hard to see how those on this thread can defend it as rational.

Are CPU's even marketed anymore? People just look at i3/i5/i7. The funny thing is Intel thought "Netburst" and high GHz would sell CPU's and then their new models came out that beat them in every metric at lower clock speeds so what did they do? Model numbers!

Besides, how many 52 core SKU's do you think there will be? I'm counting DIY since those people should know better.

LOL. I think AMD did it first to combat Intel's Netburst blue man group onslaught 😉.

Lisa Su confirmed both that Venice is on 2nm and that it has taped out for a while.

Yes she did. She confirmed it was on N2 not N2P and she confirmed Venice is on N2, not desktop or latptop. Zen 5 Turin was on N3E while destkop and laptop were on N4P (enhanced N5).

Following on with this, N2 for server and N3P for high volume makes sense. Doesn't mean it is how it will be, but it does match history and is sensical.

The point is that the Venice that CSPs are currently testing could be the dense version only and thus cant be used as proof that non-dense CCDs use 2nm or will be released in the same time frame as the dense.

This is true. At least it does make some sense that the non-dense would use 2nm from a POV of it's a power bound server product that has relatively low volume and high margins.

Desktop and laptop .... not so much.

The only Venice that Lisa mentioned officially was "up to" 256 core dense version, period, which is definitely the 2nm version. That doesnt negate the possibility that non-dense versions might not be using 2nm, unless someone has something more than what I saw, which is this:

Agree.

The remaining 270 pages are (wrongly?) speculating that server zen p (non-dense) ccd is on 2nm (despite the precedence of zen 5)

Lots of it. As I said above, I can see N2 (not N2P) for all Turin variants as it has a good deal of financial good sense to it. It's the high volume stuff I find harder to believe.

 

[inquiss]

The remaining 270 pages are (wrongly?) speculating that server zen p (non-dense) ccd is on 2nm (despite the precedence of zen 5)

Goddammit read the other pages. Zen 5 was meant to be on N3 but the node was borked so they back ported. There is already a precedent for AMD going for the latest node..

 

[jpiniero]

Goddammit read the other pages. Zen 5 was meant to be on N3 but the bide was booked so they back ported. There is already a precedent for AMD going for the latest node..

If by booked you mean "they didn't think N3B was worth it", then perhaps.

 

[adroc_thurston]

Zen 5 was meant to be on N3 but the bide was booked so they back ported

No, N3 (the OG) just looked like a total trainwreck.

If by booked you mean "they didn't think N3B was worth it", then perhaps.

Not "worth it", N3b wasn't working for a while.

 

[inquiss]

No, N3 (the OG) just looked like a total trainwreck.

Not "worth it", N3b wasn't working for a while.

Yeah edited my note. Meant "borked"

 

[Joe NYC]

Following on with this, N2 for server and N3P for high volume makes sense. Doesn't mean it is how it will be, but it does match history and is sensical.

This is true. At least it does make some sense that the non-dense would use 2nm from a POV of it's a power bound server product that has relatively low volume and high margins.

Desktop and laptop .... not so much.

I wonder if AMD just comes out with AM5 version of Medusa MDS1 die and sells it for low end desktop. It is 4+4 cores. Good enough low end desktop such as substitute for 9600. That would by your N3P desktop.

These APUs usually come out with some delay. We will see if this time is different.

But the full, high end desktop will be based on 12 core N2 CCD.

 

[MS_AT]

So leaving aside pointless process discussions, here are first compiler patches https://sourceware.org/pipermail/binutils/2025-November/145449.html

Bit Matrix Multiply seems like something new.

 

[Kryohi]

So leaving aside pointless process discussions, here are first compiler patches https://sourceware.org/pipermail/binutils/2025-November/145449.html

Bit Matrix Multiply seems like something new.

Interesting, those seem to be targeting crypto stuff or some very specific algorithms instead of ML stuff, as I understand it

 

[DrMrLordX]

How about reasoning then? Is that also ridiculous?

Yes, given the circumstances (replying to a leaker that can't/won't verify his sources, or in the case of Venice being in the hand of cloud service providers, ignoring/forgetting that Dr. Su already told us that Venice is in the hands of cloud service providers. Likely AO silicon).

The point is that the Venice that CSPs are currently testing could be the dense version only and thus cant be used as proof that non-dense CCDs use 2nm or will be released in the same time frame as the dense.

Or they could be the 96c standard Venice. Or they could be both.

The only Venice that Lisa mentioned officially was "up to" 256 core dense version, period, which is definitely the 2nm version. That doesnt negate the possibility that non-dense versions might not be using 2nm, unless someone has something more than what I saw, which is this:

We have no evidence or leaks for N3P/N3X Venice.

Yeah edited my note. Meant "borked"

 

[luro]

FP16 on desktop

https://twitter.com/x/status/1986964967858245946

 

[DrMrLordX]

@luro

That's interesting. There's Venice and Venice-d on both SP7 and SP8 . . .

 

[Josh128]

FP16 on desktop

https://twitter.com/x/status/1986964967858245946

Interesting about the process claims, they look a bit sus. Even Venice D on N2P? That makes no sense. Why would you want to use a less dense process for the most dense CPU you've ever built?

More interesting still is that we now have a CPUID entry for 64 core Zen 5 TR, but the rumored 9850X3d and the 9950 2X3D/X3D2 are nowhere to be found. Unfortunate. I was still hoping they were real this time.

https://twitter.com/x/status/1977637838364745788

 

[CouncilorIrissa]

Interesting about the process claims, they look a bit sus. Even Venice D on N2P? That makes no sense. Why would you want to use a less dense process for the most dense CPU you've ever built?

More interesting still is that we now have a CPUID entry for 64 core Zen 5 TR, but the rumored 9850X3d and the 9950 2X3D/X3D2 are nowhere to be found. Unfortunate. I was still hoping they were real this time.

https://twitter.com/x/status/1977637838364745788

Not sure if Venice Dense actually uses N2P, but I don't think TSMC said anything about N2P being less dense than vanilla N2.
It's not the N3E/N3B situation.

 

[adroc_thurston]

Interesting about the process claims, they look a bit sus. Even Venice D on N2P? That makes no sense. Why would you want to use a less dense process for the most dense CPU you've ever built?

a) it's whatever custom DTCO'd soup AMD uses
b) N2p isn't any less dense than N2. Neither actually offers the tall cell lmao

 

[ETI4711]

Not only does this say "up to 256 cores", it also says "2nm · Zen 6". Not "down to 2nm · Zen 6". There is no mention of a 3nm variant of Venice anywhere, neither in the "Advancing AI 2025" presentation on June 12, nor in

Yes.

All AMD statements mentioning the node in which Zen 6 is produced say “2 nm.”

There is no statement from AMD saying that Venice would be 2 nm and 3 nm. That was different for Zen 5

I repeat myself: https://news.mynavi.jp/techplus/article/20250822-3412896/4

Q: By the way, CEO Lisa Su has already introduced the core of the Zen 6-based EPYC product manufactured on TSMC N2 (2nm process) as "Venice" (development code name). Why Venice?

David McAfee: What do you mean?

Q: Venice was the code name for the Athlon 64 with 512KB L2 and manufactured on a 90nm SOI process. You joined AMD in 2006, when Venice-based Athlon 64s were still on the market, right?

David McAfee: I see. We transitioned the original Venice to TSMC's 2nm (laughs).

Seriously, as you know, we use the same processors for our servers and desktops, so we expect the same architecture that Lisa showed with Venice to be available on the desktop.

 

[ETI4711]

a) it's whatever custom DTCO'd soup AMD uses
b) N2p isn't any less dense than N2. Neither actually offers the tall cell lmao

What do you mean with tall cell?
N2P has two cell hights 130 nm (High density) and 156 nm (High speed)

 

[Fjodor2001]

There is no statement from AMD saying that Venice would be 2 nm and 3 nm. That was different for Zen 5

Assuming that will be the case, why will they choose different policy for Zen6 vs Zen5? Why use different nodes per CPU type for Zen5 but not for Zen6? I assume there was some reason different nodes were used for Zen5.

 

[ETI4711]

Assuming that will be the case, why will they choose different policy for Zen6 vs Zen5? Why use different nodes per CPU type for Zen5 but not for Zen6? I assume there was some reason different nodes were used for Zen5.

Perhaps because SRAM does not scale for N3E?

Zen 5 dense has only 2 MByte L3 per core so was not that hard impacted.

 

[adroc_thurston]

What do you mean with tall cell?
N2P has two cell hights 130 nm (High density) and 156 nm (High speed)

H156 is a normal perf cell.
Real HP stuff sits at N2x and H174 zoom zoom offering.

I assume there was some reason different nodes were used for Zen5

Yeah N3 exploded.

Perhaps because SRAM does not scale for N3E?

No it's because N3 was dead.