Speculation: Ryzen 4000 series/Zen 3

[uzzi38]

With the annual cadence already in place and APUs always coming last, why would AMD do two distinct APU designs in one cycle instead leaving that for the next round of updates? In one more year we'll see an APU based on Zen 3 + RDNA anyway.

I don't know, but the driver code don't lie. Van Gogh is heavily based off of Renoir, but is gfx1030.

Apparently Komachi did a write up on Reddit: https://www.reddit.com/user/Komachi_ENSAKA/comments/ea7rm3/van_gogh_is_first_rdna_gfx10_apu/

 

[soresu]

With the annual cadence already in place and APUs always coming last, why would AMD do two distinct APU designs in one cycle instead leaving that for the next round of updates? In one more year we'll see an APU based on Zen 3 + RDNA anyway.

Renoir and Dali were supposed to come in the same year on that old roadmap with the monster truck on it.

 

[uzzi38]

Dali is 2c 4t, heavily based off of RAVEN2.

Probably just an updated media and display engine, still Zen or maybe Zen+ now.

 

[moinmoin]

I don't know, but the driver code don't lie. Van Gogh is heavily based off of Renoir, but is gfx1030.

Apparently Komachi did a write up on Reddit: https://www.reddit.com/user/Komachi_ENSAKA/comments/ea7rm3/van_gogh_is_first_rdna_gfx10_apu/

All the talks on reddit are about it being a custom APU potentially for Apple. So far none of the AMD CPU-Apple rumors became true.

Dali is 2c 4t, heavily based off of RAVEN2.

Probably just an updated media and display engine, still Zen or maybe Zen+ now.

In any case it's the next low power ("value mobile") APU, in line with Raven2 indeed.

Btw. all Zen APUs up to now are technically Zen+ or newer microcode wise. They differ from desktop/server chips in still using older process nodes.

 

[uzzi38]

On the Apple side, you're right, only this time AMD's GPU driver code in MacOS was updated recently to include Raven Ridge, Picasso, Renoir and most importantly - Van Gogh. This time around, there's a bigger chance. Not the biggest, but bigger.

To clarify the Dali comment, I mean the following comment can be found in drivers:

'Dali is an ASIC based off of RAVEN2'.

It'll take me a while to find it again, but it's pretty cut and dry what Dali is.

 

[NostaSeronx]

'Dali is an ASIC based off of RAVEN2'.

It'll take me a while to find it again, but it's pretty cut and dry what Dali is.

"Dali is a new asic revision based on raven2" => https://lists.freedesktop.org/archives/amd-gfx/2019-September/039776.html

However, there is some bits point out it isn't actually Raven2;
"We only want to load DMCU FW on Picasso and Raven 2, not on Raven 1." // ((DMCU = Display Micro-Controller Unit))
//
Dali is forced to be Raven2, when it says it is Renoir =>
/* TEMP: this check has to come before ASICREV_IS_RENOIR */
/* which also incorrectly returns true for Dali */

RAVEN1_F0 is the same generation as RENOIR_A0.

----
Original Dali was 7nm EUV => 2x Zen3 cores + 8 RDNA CUs(4 Dual-CUs?)

The current model has implied Vega 8/Vega 6/Vega 3 under Raven1_F0. So, it is likely that Raven1_F0 while a backport will continue to have 8 CUs.

 

[uzzi38]

I said the same thing mate. Display and media engines are updated to the same as RDNA (I forget if RDNA1 or RDNA2, but same as Renoir).

Thanks for the link though.

 

[soresu]

4 Dual-CUs?

Workgroup Processors, or WGP's is AMD's terminology.

 

[amd6502]

Workgroup Processors, or WGP's is AMD's terminology.

Now somebody is speculating that Renoir might be a 12 or 13 CU part, which by the names they found in the product master list implies an octacore APU (with Ryzen9 flashship in mobile and Ryzen7 flagship on AM4). The AM4 desktop TDP's range from 35W to 65W while the notebook parts range from 15W to 45W, including a 15W mobile (implied) octacore.

This 15W top bin 8c would probably be hard to do if Renoir was an MCM (with IO hub integrated into the iGPU and re-use of the existing 8c chiplets), even if the GPU/IO chiplet is on 7nm. So most likely that's gotta be monolithic with halved L3 (possibly quartered).

https://www.reddit.com/r/Amd/comments/ebxsvh

Sounds like a very nice line of products right there, wow.

 

[Gideon]

Now somebody is speculating that Renoir might be a 12 or 13 CU part, which by the names they found in the product master list implies an octacore APU (with Ryzen9 flashship in mobile and Ryzen7 flagship on AM4). The AM4 desktop TDP's range from 35W to 65W while the notebook parts range from 15W to 45W, including a 15W mobile (implied) octacore.

This 15W top bin 8c would probably be hard to do if Renoir was an MCM (with IO hub integrated into the iGPU and re-use of the existing 8c chiplets), even if the GPU/IO chiplet is on 7nm. So most likely that's gotta be monolithic with halved L3 (possibly quartered).

https://www.reddit.com/r/Amd/comments/ebxsvh

Sounds like a very nice line of products right there, wow.

IMO there was little question that AMD could have done 8 cores @ 15W, if Intel was able to squeeze 6 cores into the 15W envelope, but it's nice to see that they are indeed doing it. I've been banging the 8-core Renoir drum for quite a while

Overall a very strong lineup, the only thing where I expected more is the CU count (particularily as this is still Vega), as this is 12-13 tops, which is almost the same as Raven Ridge's 10-11. They will have higher clocks for sure and also LPDDR4X, but since it isn't Navi it will be a tough competition against Tiger Lake. It will probably lose, as Tiger doubles the EU count once more and has LPDDR5.

 

[uzzi38]

Tiger is 1.5x the EU count, 2x the perf, but otherwuse you're correct.

Renoir is aimed to yeet Comet Lake-U out of relevancy though more than anything else. The Tiger Lake competitor is either Van Gogh or the 2021 APU.

 

[tomatosummit]

Now somebody is speculating that Renoir might be a 12 or 13 CU part, which by the names they found in the product master list implies an octacore APU (with Ryzen9 flashship in mobile and Ryzen7 flagship on AM4). The AM4 desktop TDP's range from 35W to 65W while the notebook parts range from 15W to 45W, including a 15W mobile (implied) octacore.
.

The BXX numbering is more likely to be a performance tier instead of directly relating to CU count. Every leak before has said 16-20cu and on a process shrink the compute units are going to shrink very well so I don't think they'll cut that many.
My crazy out there guess is that B12 is a new performance tier brought about by the new fp6 socket allowing some kind of on package memory or lpddr4 which is why the am4 parts don't have that. I was even wondering if a 64bit gddr6 2x package would be easier to achieve than an HBM package, as that low bandwidth cheap non-interposer hbm2 never appeared. FP6 is a new socket and hopefully offers something good, budget designs could just skimp on the features like they usually do.

There's been no news about renoir MCM and there's not really a point in gimping the l3 cache if they use the current ccd. I'm more curious about how much extra die space would be needed on an IO/gpu die if the single cpu complex is separate. epyc2 and ryzen3000 have a huge amount of die space because of that and I don't think a mainstream soc would manage all of that extra space.

 

[uzzi38]

The BXX numbering is more likely to be a performance tier instead of directly relating to CU count. Every leak before has said 16-20cu and on a process shrink the compute units are going to shrink very well so I don't think they'll cut that many.
My crazy out there guess is that B12 is a new performance tier brought about by the new fp6 socket allowing some kind of on package memory or lpddr4 which is why the am4 parts don't have that. I was even wondering if a 64bit gddr6 2x package would be easier to achieve than an HBM package, as that low bandwidth cheap non-interposer hbm2 never appeared. FP6 is a new socket and hopefully offers something good, budget designs could just skimp on the features like they usually do.

There's been no news about renoir MCM and there's not really a point in gimping the l3 cache if they use the current ccd. I'm more curious about how much extra die space would be needed on an IO/gpu die if the single cpu complex is separate. epyc2 and ryzen3000 have a huge amount of die space because of that and I don't think a mainstream soc would manage all of that extra space.

Not every leak has said 16-20. Only AdorkedTV.

Here's something from someone with an actually good track record unlike Jim:

https://twitter.com/x/status/1158345472873914368

 

[NostaSeronx]

There is low hanging fruit! MCM without I/O die.

209.78 = RV0 * (331(RVII) / 486(RX64)) => 142 mm2
77+77+125 = 279 mm2 <-- One IOD + Two CCDs
142+142 = 284 mm2 <-- Two Monolithic dies interconnected via Renoir's EPYC(Zeppelin)-style Infinity Fabric.

Allowing for 8-cores(4+4), 24 CUs(12 CU+12 CU)((Up 20% from 10 CUs each)), 256-bit DDR4 memory, 2x VCN load, etc.
Maybe, phy salvaing, 256-bit at 3.2 GHz and 128-bit @ >4 GHz, etc.

 

[uzzi38]

There is low hanging fruit! MCM without I/O die.

209.78 = RV0 * (331(RVII) / 486(RX64)) => 142 mm2
77+77+125 = 279 mm2 <-- One IOD + Two CCDs
142+142 = 284 mm2 <-- Two Monolithic dies interconnected via Renoir's EPYC(Zeppelin)-style Infinity Fabric.

Allowing for 8-cores, 24 CUs(12 CU+12 CU)((Up 20% from 10 CUs each)), 256-bit DDR4 memory, 2x VCN load, etc.

For Renoir? No no no, no MCM. Renoir is 100% monolithic. Absolutely not. Nope. Nada. Nai wa~

Not a sensible choice for mobile. MCM is extra idle power draw even without an I/O die, and most importantly, AMD don't want to go through the same routing mess they had in AM4 on FP6.

 

[NostaSeronx]

Renoir is 100% monolithic.

It is 100% monolithic. While, also capable of using the Infinity Fabric integrated in Renoir for IFOP to another monolithic Renoir die.

There is no issues with power, since the actual increase isn't massive. The die isn't going from 4c to 8c or 10 cu to 20 cu. So, it can maximize on the >50% lower power.
Ryzen 3700u => 15W, two Renoir dies of the same clock speed => 6.5W+6.5W = ~15W

 

[uzzi38]

It is 100% monolithic. While, also capable of using the Infinity Fabric integrated in Renoir for IFOP to another monolithic Renoir die.

There is no issues with power, since the actual increase isn't massive. The die isn't going from 4c to 8c or 10 cu to 20 cu. So, it can maximize on the >50% lower power.
Ryzen 3700u => 15W, two Renoir dies of the same clock speed => 6.5W+6.5W = ~15W

Overall power increase isn't high, you're correct, but IFOP links are like an extra 0.3W each, which is extra idle power draw.

Big no-no for mobile.

 

[amd6502]

Likely all the 15w 8c are elite bin (low volume), and 15w 6c are high bin.

Desktop and 45W bga (mobile gaming and oem desktop and all-in-1) parts should provide a lot of volume to support a decent number of mobile elite bins.

I really would not have guessed they would do Zen2 with a monolithic 8c, but this is a great surprise. In retrospect, this is a brilliant complement to the current product lines. Dr Su and her teams are true geniuses.

I think the GPU is nicely sized for what mainstream DDR4 can provide. For the non-15W parts (particularly the desktop 65W+ parts) the iGPU clock can be quite a bit higher thanks to 7nm's effiency advantage over 12nm. Picasso 11CU is already maxed out memory wise.

It also wouldn't surprise me if we see a 95W desktop flagship; that will let a decent amount of power go through the iGPU.

 

[uzzi38]

Honestly speaking, it should be too much of a surprise that Renoir is monolithic. AMD specifically said no Zen 2 chiplet APUs a long, long while back to Anandtech afaik.

Also, no need to crank up clocks so high for the iGPU on desktop, memory bandwidth might be lower there because of no LPDDR4X - no guarantee Renoir can run DDR4 at 1:1 at such high clocks.

 

[Shivansps]

Now somebody is speculating that Renoir might be a 12 or 13 CU part, which by the names they found in the product master list implies an octacore APU (with Ryzen9 flashship in mobile and Ryzen7 flagship on AM4). The AM4 desktop TDP's range from 35W to 65W while the notebook parts range from 15W to 45W, including a 15W mobile (implied) octacore.

This 15W top bin 8c would probably be hard to do if Renoir was an MCM (with IO hub integrated into the iGPU and re-use of the existing 8c chiplets), even if the GPU/IO chiplet is on 7nm. So most likely that's gotta be monolithic with halved L3 (possibly quartered).

https://www.reddit.com/r/Amd/comments/ebxsvh

Sounds like a very nice line of products right there, wow.

Sounds like a downgrade to me.

10-11CUs for Ryzen 7
8-9CUs for Ryzen 5
6 CUs for Ryzen 3
3-4CUs for probably another Athlon.

If is Vega, is a downgrade. They are probably going lever on the better cpus cores and improved memory/graphics speed to at least match Piccaso performance. Huge letdown.

Also whats this:

• Picasso 15D8_REV_CD AMD Radeon(TM) Vega 2 Graphics
• Picasso 15D8_REV_93 AMD Radeon(TM) Vega 1 Graphics

 

[soresu]

If is Vega, is a downgrade.

How so?

Both Raven Ridge and Picasso are Vega 14 and 12nm.

 

[amd6502]

Not really. I would say 12-13CU for the octacores (Ryzen9mobile, Ryzen7DT) and some Ryzen7mobile.

11-8CU for the hexacores (which range from Ryzen5 DT and Ryzen5-7 mobile) and lower bin 8c Ryzen7 DT.

3-6CU for the few rare quadcore parts and other bottom bin parts.

And Vega frequencies would be at least 10% higher (usually ~20% higher) on any average or better bin APU. So all in all I would expect an upgrade or even at least.

Sounds like a downgrade to me [....]
6 CUs for Ryzen 3
3-4CUs for probably another Athlon.

I doubt Athlons will be derived from the 8c die salvage. If they are, they might be GPU-less quadcores. I think they would be better off using the Phenom brand for CPU only parts to avoid confusion with the Athlon APUs.

As for what's Vega1 and Vega2, it may be something other than 1-2CU parts. If it is 1-2CU parts, it could be die salvage for an embedded part.

 

[Shivansps]

Not really. I would say 12-13CU for the octacores (Ryzen9mobile, Ryzen7DT) and some Ryzen7mobile.

11-8CU for the hexacores (which range from Ryzen5 DT and Ryzen5-7 mobile) and lower bin 8c Ryzen7 DT.

3-6CU for the few rare quadcore parts and other bottom bin parts.

And Vega frequencies would be at least 10% higher (usually ~20% higher) on any average or better bin APU. So all in all I would expect an upgrade or even at least.

Im talking about desktop specifically, they are reducing the number of CUs in Vega for the products they are replacing. Taking the advantage of increased CPU performance and clocks to not look so bad. Thats still a downgrade. There is no way to defend this.

The Vega 3-4 is probably a quad core Athlon based on Renoir, probably at $75-80. But they could use another name.

How so?

Both Raven Ridge and Picasso are Vega 14 and 12nm.

AMD Ryzen 5 3400G Vega 11 to Ryzen 5 Vega 8-9 in Renoir
AMD Ryzen 3 3200G Vega 8 to Ryzen 3 Vega 6 in Renoir

Thats a downgrade, unless they are pairing a Renoir Ryzen 7 as 3400G replacement (not gonna happen).

 

[uzzi38]

The only sku missing from that would be the Renoir Ryzen 9 w/12-13CU sku. You'd still have the 11CU one.

 

[Shivansps]

The only sku missing from that would be the Renoir Ryzen 9 w/12-13CU sku. You'd still have the 11CU one.

At a higher price... If they are going to replace the Vega 8 3200G for a Vega 6 one, thats a downgrade, if they are going to replace the Vega 11 3400G for a Vega 8-9 one thats a downgrade as well... There is no way for the Vega 11 Ryzen 7 Renoir to be the 3400G replacement.

This would already be bad with Navi RDNA cores, but with Vega? is just unacceptable. I hope reviewers trashes AMD a lot of this. I still belive there is a chance that the info is wrong, is just too bad to be true.