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IntelUser2000

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AMD Ryzen 5 3400G Vega 11 to Ryzen 5 Vega 8-9 in Renoir
AMD Ryzen 3 3200G Vega 8 to Ryzen 3 Vega 6 in Renoir

Thats a downgrade, unless they are pairing a Renoir Ryzen 7 as 3400G replacement (not gonna happen).
Whatever they call the final product, its just marketing tricks.

So its possible that Renoir Ryzen 7 is higher priced than Picasso Ryzen 5. But really if they do that then all they are doing is raising the price.

Just like how we got Core "i9" when they could have called it Core i7 and made it the same product. But because i9 never existed it sounds even more premium.

Or Nvidia's practice of xx60 series costing $100 more. and xx80 Ti costing like Titans.

Early leaks had Renoir GPU at 1.75GHz. That's 25% higher than Picasso. The clocks loosely seem to follow discrete parts.
 

soresu

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Dec 19, 2014
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At a higher price... If they are going to replace the Vega 8 3200G for a Vega 6 one, thats a downgrade, if they are going to replace the Vega 11 3400G for a Vega 8-9 one thats a downgrade as well... There is no way for the Vega 11 Ryzen 7 Renoir to be the 3400G replacement.

This would already be bad with Navi RDNA cores, but with Vega? is just unacceptable. I hope reviewers trashes AMD a lot of this. I still belive there is a chance that the info is wrong, is just too bad to be true.
7nm clock increases?
 
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soresu

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Early leaks had Renoir GPU at 1.75GHz. That's 25% higher than Picasso. There's that. The clocks loosely seem to follow discrete parts.
Not exactly - Vega 64 was 1.54 Ghz+, 14nm Vega 11 was 1.3 Ghz on the 2400G.

240 mhz may not be much, but I imagine that Vega 11 is more closely following the optimal position on the bell curve of Vega.
 

IntelUser2000

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Not exactly - Vega 64 was 1.54 Ghz+, 14nm Vega 11 was 1.3 Ghz on the 2400G.
Haha. Honestly you are nitpicking at the offhanded comment I made. 3400G is 1.4GHz BTW.

The Radeon VII is at 1.75GHz for boost.
 
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soresu

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Haha. Honestly you are nitpicking at the offhanded comment I made. 3400G is 1.4GHz BTW.

The Radeon VII is at 1.75GHz for boost.
I was comparing at same ish process for Vega 64 and 2400G. 12nm gives that 100mhz boost to 1.4Ghz.

Neither Vega 64 nore VII represent good efficiency as far as Vega goes is the point I was making, best to stick with APU's as ref points.

Best case scenario we can take that 1.75 Ghz number to represent 200mhz higher than 12nm, given Vega 20 also has extra stuff in there for FP64 rate and AI/ML instructions.

That gives about 1.6 Ghz for optimal conditions, though I would predict closer to 1.55 Ghz.
 
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Thunder 57

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Aug 19, 2007
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Sorry about giving you a hard time. You still aren't changing my mind though.

This doesn't look good for x86.
You know how long I've been hearing that?

So you would disclose major next gen feature at presentation of current product. Great idea. This never happened in history of Intel neither AMD. That's pure naivety. Leaving blank is definitely acceptable however it would feed speculations. AMD doesn't lie if they say Zen 3 will support SMT2. Simply because SMT4 CPU supports SMT2 mode too. On the Zen3 uarch revelation AMD could just say: "Wait, and one more thing, Zen3 also supports SMT4". That's why the presentation says nothing about SMT4 for Zen 3.
We knew about chiplets long before Zen 2. That's a much larger shift then SMT4. We knew plenty about Netburst and K7 before they came out. How long did we know about 64 bit in K8 before it came out? That was huge. Extending an ISA vs adding a couple more threads/core. So to say AMD/Intel has never disclosed a major next gen feature that far in advance is flat out false. AMD announced x86-64 a full three years before it came out. K7 and Netburst were about a year each before release. I'm willing to hear your arguments, but make sure they are accurate if you want to change mine (or anyone's) mind.

BTW: Look how x86 has terribly low IPC in compare to ARM. The fastest Ryzen 3950X @ 4.6 Ghz is beaten by iPhone CPU A13 at just 2.6 GHz. AMD needs to push hard in servers and SMT4 is the lowest hanging fruits there.

IPC calculations of SPECint2006:
  • - 9900K .... 54.28/5 GHz = 10.86 pts/GHz
  • - 3950X .... 50.02/4.6 GH = 10.87 pts/GHz
  • - A76 ........ 26.65/2.84 GHz = 9.38 pts/GHz
  • - A77 ........ 33.32/2.84 GHz = 11.73 pts/GHz ...... +8% IPC over 9900K
  • - A11 ........ 36.80/2.39 GHz = 15.40 pts/GHz .... +42% IPC over 9900K
  • - A12 ........ 45.32/2.53 GHz = 17.91 pts/GHz .... +65% IPC over 9900K
  • - A13 ........ 52.82/2.65 GHz = 19.93 pts/GHz .... +83% IPC over 9900K
  • - A14 ........ 66.00/3.00 GHz = 22.00 pts/GHz (estimated +10%IPC)
  • - Zen3 ...... 60.00/4.60 GHz = 13.04 pts/GHz (estimated +20% IPC)
OK, so your just inventing a metric (pts/GHz) using just SPEC2006 and are using that to claim ARM is far superior to x86. IPC on its own means nothing. GHz on its own means nothing. ARM excels in low power performance. x86 does well in overall performance. Can these lower power ARM cores scale up to 32 or 64 core CPU's without blowing up power usage? I don't know. I'd like to see them try.

Also, what makes SMT4 the lowest hanging fruit out there. You just happen to know this? I might buy that argument if we were still using quad core server chips. It worked out alright for POWER, and still does. But with the massive number of cores available today, I'm not so sure SMT4 matters as much as you think it does. Even then, I expect it would only benefit servers. I think AMD would prefer to spend die space on features that benefit the whole product stack.

You maybe would have a point here except if you go back and look at the presentation, did the slide say that Zen3 will support SMT2 or did it say that Zen3 will have a max core/thread count of 64 cores / 128 threads?
It said "Max cores / threads". That should be case closed. Apparently not...
Maximum:
as great, high, or intense as possible or permitted.

Well, I enjoy reading Nosta and Rich's comments. Zen4 is still in design afaik. I don't think it's too much of a stretch that Zen4 has some form of 4-way MT.


For Zen3 to have it was much more of a hope than an expectation.

And i did mostly agree with you folks. Namely, that underutilization of pipes @ SMT2 isn't going to be a problem at least for desktop. So most likely the same power efficiency recipe is going to be applied as was quite successfully done during the Steamroller → XV upgrade, and also in Zen1, namely heavy gating and powering down of unused circuits, and lots of sensors to allow minimized voltage. Maybe also work on IF and SoC uncore savings. Those things combined with the substantial savings from 7nm should get them pretty far.

I think they will have a killer mobile APU and I hope they skip straight to Zen3 for their monolithic mobile focused APU.

Between Zen2 and Zen3 (or just Zen3 if Zen2 skips monolithic) I think they have enough budget to have two APU dies; small and large. It would make sense for small die to arrive first and wait a bit on 7nm to mature. Small die being quadcore with ~8CU (possibly as low as 6CU) and with the big die being octacore with ~16CU.

A big core 8c APU is going to draw some considerable wattage, even on 7nm. But they can bin these so that most mobile end up being 6c while purposing the bulk of 8c's to desktop.

Also, the software side for minimizing wattage while unplugged should be simple as most real OS's support hotplug CPU. It's a one liner in linux to power down a core.






True, but wattage also scales linearly (or affinely, counting uncore wattage) with cores.

So if the uncore and minimally active iGPU account for 1/3 the wattage, ~5W (on a 15W mobile quadcore APU), then the octacore equivalent is going to want to be a 25W tdp part.

I do think/hope that they will have a top bin 8c with 15W tdp and that they can also get good near idle wattage with some software tweaks.
I enjoy their posts as well, though more for their entertainment value. I agree with a lot of what you say. Getting IF to burn less power could pay dividends. I don't see how AMD skips Zen 2 with Renoir about to come out. I really hope the LPDDR4X rumors are true. That could be a potent APU if so. What I don't agree with is why SMT4 with Zen 3 would be a hope at all. It certainly wasn't an expectation. It would be interesting to see just for the fact that we'd have hard data, but I don't think it's worth the cost.

Sounds like a downgrade to me.

10-11CUs for Ryzen 7
8-9CUs for Ryzen 5
6 CUs for Ryzen 3
3-4CUs for probably another Athlon.

If is Vega, is a downgrade. They are probably going lever on the better cpus cores and improved memory/graphics speed to at least match Piccaso performance. Huge letdown.

Also whats this:
I doubt AMD would come out with a new product that was a downgrade. That'd be... foolish considering current management is pretty smart. AMD already has problems keeping Vega fed though. Until they figure out the memory bandwidth problem, that will be the case. I'd therefore expect them to put more work into the CPU side until that memory bandwidth gets sorted out.
 
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uzzi38

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Of course it wouldn't be a downgrade. You're looking at an upgrade from Zen+ to Zen 2 cores, and due to the monolithic design will have lower memory latency than Matisse.

But you're replying to the kind of guy that calls something unacceptable 6 months before there's even a chance of the product coming to market, long before the final specifications are finalised, and is going on a tantrum about how it's not what he wants and that it should be trashed. Why bother?
 

Thunder 57

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Aug 19, 2007
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I was just reading through that x86-64 article in my previous post, and there's a very interesting quote.

Unfortunately with this comes a major downside, by building on the x86 ISA yet again AMD is still bringing along with them all the added baggage that comes with the x86 ISA. We asked AMD about this noticeable downside and their stance on the issue is simple, they believe that "performance has less to do with instruction set and more to do with implementation," which is what they're banking on with x86-64.
Interesting how all these years later, people are still trying to make that point. Because we got the ARM fans or the RISC-V fans or whoever trying to crap on x86. x86 is sill around. That's what I meant when I said "You know how long I've been hearing that?".
 

Thunder 57

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Aug 19, 2007
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Of course it wouldn't be a downgrade. You're looking at an upgrade from Zen+ to Zen 2 cores, and due to the monolithic design will have lower memory latency than Matisse.

But you're replying to the kind of guy that calls something unacceptable 6 months before there's even a chance of the product coming to market, long before the final specifications are finalised, and is going on a tantrum about how it's not what he wants and that it should be trashed. Why bother?
Ha, I kind of skimmed most of the last page. I see what you mean. APU's have always lagged GPU wise going back to Llano. Why would Vega suddenly be a letdown? Mobile Vega is pretty good. Not the power hog Vega 64 is. Calling for a products head before there are even reviews seems... ill-advised.

Honestly where AMD needs their APU line to be more competitive is on the CPU side anyway. Vega 10 still holds it's own against Ice Lake despite a massive bandwidth disadvantage. Pair it with Zen 2, a couple more CU's, and much faster RAM and it would make a great followup for Picasso in Surface.
 

Antey

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Hello! I have some questions if you don't mind :)

is it possible that renoir is a 2x ccx = 8 cores 16 thread apu with 16mb L3 cache instead of 32? raven and picasso are both 4 cores 8 threads with 'just' 4mb of cache compared to pinnacle and summit ridge that both have 8mb of cache per ccx. if yes, should we expect a bit of a less ipc compared to matisse? if yes, again, how much less ipc would it be?

i understand that ipc is just the average of the cpu performance on many different workloads. how big would be the effect on gaming or the typical productivity workloads (encoding, rendering, office, etc) that anandtech and others like to test?

Do you think that renoir will have just x8 pcie lanes for an external gpu like picasso does? pcie 4.0?

edit: wrote ram instead of cache :tearsofjoy:
 
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uzzi38

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Oct 16, 2019
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Yes it is possible, but I don't expect an IPC decrease. Renoir is monolithic, whereas Matisse is chiplet based, so it should also sport lower memory latency vs Matisse.
 

Shivansps

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Sep 11, 2013
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Of course it wouldn't be a downgrade. You're looking at an upgrade from Zen+ to Zen 2 cores, and due to the monolithic design will have lower memory latency than Matisse.

But you're replying to the kind of guy that calls something unacceptable 6 months before there's even a chance of the product coming to market, long before the final specifications are finalised, and is going on a tantrum about how it's not what he wants and that it should be trashed. Why bother?
Im talking about the data that we know, i said could be wrong, in fact i hope it is wrong. But a overclocked Zen 2 Vega 6 APU as a replacement Zen+ Vega 8 APU is just unacceptable if it happens, the whole point in a APU is the IGP in combination with the cpu cores, giving the same gpu and making it smaller to match performance and not provide any gains is unacceptable.
 

Antey

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Yes it is possible, but I don't expect an IPC decrease. Renoir is monolithic, whereas Matisse is chiplet based, so it should also sport lower memory latency vs Matisse.
Maybe a bit higher performance in games (lower latency) but a bit lower performance in productivity workloads (that benefit from more cache)? i'm wondering how much noticeable will it be if that is the case. i don't expect much personally, maybe 1-5% depending on the game, i dont know about the others. does L3 cache increase the performance in productivity workloads that much? why would they increase cache again in vermeer? i'm saying it because i saw that slide of zen 3 with 32 ''+'' of L3 per CCD cache in it.

maybe it's because it's cheaper to just not redesign it and have 1 design and make dies that work for server or desktop even if the extra cache is not an improvement for desktop. and they just get the better ones and put them in server designs and the not that good ones in desktop, etc.
 

lobz

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Feb 10, 2017
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Maybe a bit higher performance in games (lower latency) but a bit lower performance in productivity workloads (that benefit from more cache)? i'm wondering how much noticeable will it be if that is the case. i don't expect much personally, maybe 1-5% depending on the game, i dont know about the others. does L3 cache increase the performance in productivity workloads that much? why would they increase cache again in vermeer? i'm saying it because i saw that slide of zen 3 with 32 ''+'' of L3 per CCD cache in it.

maybe it's because it's cheaper to just not redesign it and have 1 design and make dies that work for server or desktop even if the extra cache is not an improvement for desktop. and they just get the better ones and put them in server designs and the not that good ones in desktop, etc.
I think games benefit a lot more from the huge cache (on matisse) than from a bit lower latencies.
 

Antey

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8 cores 8 threads R7... it seems they took the intel way. i guess R9 is going to be 8C/16T, R5 6C/6T and R3 4C4T...
 

uzzi38

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If it wasn't 8c/8t, it was gonna be 6c/12t. Either way multicore perf would be more or less the same.
 

mikk

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8 cores are nice for the ULV segment but with only 8 threads not that spectacular, I would have preferred a 6/12 version. But looks like another naming scheme copy from AMD, R9 should get 8/16, possibly this is a H-version model though.
 

uzzi38

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Oct 16, 2019
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8 cores are nice for the ULV segment but with only 8 threads not that spectacular, I would have preferred a 6/12 version. But looks like another naming scheme copy from AMD, R9 should get 8/16, possibly this is a H-version model though.
Nah, they'll be able to slap 8 cores in 15W as well. And I'm fairly certain the aim is to do so.
 

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