I think it's mainly that more than 2 threads per core has been done by other CPUs, in the SPARC and Power families. Those were also focused on high IO bandwidth, much like AMD's current EPYC offerings. But AMD has to design for both consumers and servers and SMT2 is a pretty good compromise.Speculation aside, what the heck is the fascination with SMT4? Because it really hasn't been done before (or at all in x86-land)? If AMD saw a reason for it, I'm sure they'd be working on it. With the massive amount of real cores available these days, I really question how much doubling threads would help outside of very specific use cases.
Some example benchmarks from 7zip on a SPARC T5, 1 core 8 threads:
|Threads||Compression (MIPS)||Decompression (MIPS)|
As you can see the benefit diminishes.