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Speculation: Ryzen 4000 series/Zen 3

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Thunder 57

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Aug 19, 2007
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Re: Zen 3+, I do think it would be very reasonable for AMD to work on this IF they are doing Zen3 on N7P. I do not have the slightest clue if they are, but here's my rationale:

1) porting N7P to N6 w/o retooling (as I understand it) for fairly easy 5-10% improvements
2) extend the shelf life of B550/X570 and give further upgrade path
3) a nice gesture of good will, as they eschew AM4 and move on full speed ahead
4) will give them more time to work out kinks on Zen4 / AM5 (almost 2 year cycle between Zen3 release and a Zen4 release could be created - if they need it)
It was my understanding that N6 was meant as a cheap-ish way for clients on N7 to get an an upgrade path, and that N7P was superior to N6.


By contrast, N7+ uses different design rules, but also provides more benefits than N6 when compared to N7.
Of course, things may have changed.
 
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NostaSeronx

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Sep 18, 2011
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N7P was superior to N6.
N6 can be up to N5 in perf/power in RTO and NTO options. With its compatibility with N7/N7P, it also supports higher volume compared to N7+. More customers are expected to RTO and logic physical redesign NTO, than to go full N7+ redesign.

Samsung's 5LPE 6-track & 7.5-track is on-par with TSMC's N6 6-track & 7.5-track.
 
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Thunder 57

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Aug 19, 2007
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N6 can be up to N5 in perf/power in RTO and NTO options. With its compatibility with N7/N7P, it also supports higher volume compared to N7+. More customers are expected to RTO and logic physical redesign NTO, than to go full N7+ redesign.

Samsung's 5LPE 6-track & 7.5-track is on-par with TSMC's N6 6-track & 7.5-track.
One of these days you will surprise us with a source or drop a link.
 

NostaSeronx

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Sep 18, 2011
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One of these days you will give a source or drop a link.
Fusechip & semiwiki

Most of the stuff added to 5LPE was already in TSMC's N7P. The only thing it lacked was EUV and the enhanced routing efficiency/yield that it provides.

N7+ is a big shrug as most companies who wanted to go on it have dropped it for N6 instead. Technically, more room for AMD, but N7+ and N6 use the same Fab. With N6 to ramp to a higher volume than N7+.

Also, N6 might have + option to support RTOs from N7+ w/ 4 layers to N6(+?) w/ 5 layers and NTOs from 7+ to support even further optimization of the 5-track 7+ option. N6 is suppose to evolve from N5 learning, so it going to N7+ or further than it, is a given.

Also, note there is no discrete N6/6nm node on the website: https://www.tsmc.com/english/dedicatedFoundry/technology/logic.htm
Instead, it is in the N7/7nm section => https://www.tsmc.com/english/dedicatedFoundry/technology/logic.htm#l_7nm_technology
It is completely feasible that "7nm/N7" mentioned can refer to any node in the family; N7, N7P, N7+, N6
 
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inf64

Platinum Member
Mar 11, 2011
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Zen3+ is possible for APUs, not a straight GPU-less desktop parts. Zen4 looks to be early 2022 product so Zen3 parts need to hold the forth from Q4 2020 to Q4 2021. I don't see any problem with that, Zen3 will most likely be a superior desktop part to anything intel has in store (in every price bracket). Oh and there is Zen2 to cover the "lower" end of the scale, no matter how absurd that sounds right now.
 

Ajay

Diamond Member
Jan 8, 2001
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Zen3+ is possible for APUs, not a straight GPU-less desktop parts. Zen4 looks to be early 2022 product so Zen3 parts need to hold the forth from Q4 2020 to Q4 2021. I don't see any problem with that, Zen3 will most likely be a superior desktop part to anything intel has in store (in every price bracket). Oh and there is Zen2 to cover the "lower" end of the scale, no matter how absurd that sounds right now.
So where did Q4 2020 for Zen3 come from?
 

Thunder 57

Golden Member
Aug 19, 2007
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Fusechip & semiwiki

Most of the stuff added to 5LPE was already in TSMC's N7P. The only thing it lacked was EUV and the enhanced routing efficiency/yield that it provides.

N7+ is a big shrug as most companies who wanted to go on it have dropped it for N6 instead. Technically, more room for AMD, but N7+ and N6 use the same Fab. With N6 to ramp to a higher volume than N7+.

Also, N6 might have + option to support RTOs from N7+ w/ 4 layers to N6(+?) w/ 5 layers and NTOs from 7+ to support even further optimization of the 5-track 7+ option. N6 is suppose to evolve from N5 learning, so it going to N7+ or further than it, is a given.

Also, note there is no discrete N6/6nm node on the website: https://www.tsmc.com/english/dedicatedFoundry/technology/logic.htm
Instead, it is in the N7/7nm section => https://www.tsmc.com/english/dedicatedFoundry/technology/logic.htm#l_7nm_technology
It is completely feasible that "7nm/N7" mentioned can refer to any node in the family; N7, N7P, N7+, N6
Thanks for the more in depth response.
 

trexfromouterspace

Junior Member
Feb 17, 2020
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Nobody wants to use N7+ because it's not compatible with N7 designs.

N6 is compatible with N7's designs and has the same rules, so any company looking to do an iteration of an N7 or N7P product will do it on N6. It's easier to go from N7 to N6 than it is to go from N7 to N7+, and you get more out of it.

N7P is a tuned N7, no major changes.
 

NostaSeronx

Diamond Member
Sep 18, 2011
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Nobody wants to use N7+ because it's not compatible with N7 designs.

N6 is compatible with N7's designs and has the same rules, so any company looking to do an iteration of an N7 or N7P product will do it on N6. It's easier to go from N7 to N6 than it is to go from N7 to N7+, and you get more out of it.
I believe the main reason is actually there will be a N6 option that allows for: N7+ tailored-IP and N7 tailored-IP to co-exist.
N6 with N7 support risk => Q1 2020
N6 with N7+ support after N5 hits a specific volume target => Any time after Q2 2020

With the N7+ support giving an option for IP on N7/N6 to co-exist with IP built for N7+. Basically, N6 is a long-term funnel node fixing the distribution problem of having a 7nm DUV and 7nm EUV node. That are largely incompatible with each other, but with the N6 fix is now compatible with each other.

Early 2019 => N6 only supports N7.
Late 2019 => N6 is a superset of N7+.
TSMC's word => "TSMC's N6 technology provides customers with additional cost-effective benefits while extending the industry-leading power and performance from the 7nm family"
Only N7/N7+ are listed above that, which I believe is what the 7nm family is referring too.

Modes of support of the 6nm node:
{Drive 7nm into 6nm}
-> N7 to N6 retapeout => same draw
-> N7 to N6 new tapeout(New M0 routing) => new draw
{Drive 7nm+ into 6nm}
-> N7+ to N6 retapeout => same draw
-> N7+ to N6 new tapeout(New M0 routing) => new draw
{Support both 7nm&7nm+ and full 6nm designs}
-> Combined or mixed N7+/N7 tapeouts and/or completely new pure N6 tapeout.
 
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trexfromouterspace

Junior Member
Feb 17, 2020
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I believe the main reason is actually there will be a N6 option that allows for: N7+ tailored-IP and N7 tailored-IP to co-exist.
N6 with N7 support risk => Q1 2020
N6 with N7+ support after N5 hits a specific volume target => Any time after Q2 2020

With the N7+ support giving an option for IP on N7/N6 to co-exist with IP built for N7+. Basically, N6 is a long-term funnel node fixing the distribution problem of having a 7nm DUV and 7nm EUV node. That are largely incompatible with each other, but with the N6 fix is now compatible with each other.

Early 2019 => N6 only supports N7.
Late 2019 => N6 is a superset of N7+.
TSMC's word => "TSMC's N6 technology provides customers with additional cost-effective benefits while extending the industry-leading power and performance from the 7nm family"
Only N7/N7+ are listed above that, which I believe is what the 7nm family is referring too.

Modes of support of the 6nm node:
-> N7 to N6 retapeout => same draw
-> N7 to N6 new tapeout(New M0 routing) => new draw
-> N7+ to N6 retapeout => same draw
-> N7+ to N6 new tapeout(New M0 routing) => new draw
-> Combined or mixed N7+/N7 tapeout and/or completely new pure N6 tapeout.
No, you have it completely wrong. N6 is what N7+ should have been. Going from N7 or N7P to N7+, you need to rework your entire design and flow, which takes time and money. Going from N7 or N7P to N6 is a simple port.

N7+ is a dead end node that's more trouble than it's worth. If companies are going to go through the effort of creating a new design, they're going to N5/N5P, not N7+.
 

NostaSeronx

Diamond Member
Sep 18, 2011
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No, you have it completely wrong. N6 is what N7+ should have been. Going from N7 or N7P to N7+, you need to rework your entire design and flow, which takes time and money. Going from N7 or N7P to N6 is a simple port.

N7+ is a dead end node that's more trouble than it's worth. If companies are going to go through the effort of creating a new design, they're going to N5/N5P, not N7+.
The rework is redesigning for M2=CPP(7nm) to M2=(2/3)CPP(7nm+) and locking it between them. Compared to Samsung's 5LPE which supports both M2=CPP and M2=(2/3)CPP.

For example SiPearl is using Zeus which is a 7nm+ product, but it is being taped out on 6nm.
Ex: "Zeus specifically designed takes advantage of the power and area advantages of the 7nm+ process."
6nm.png

The above is an indicator to me that 7nm+ can also be ported to 6nm.

imho, It is a lot nicer on a roadmap to have 7nm/6nm/5nm compared to 7nm/7nm+/5nm. <== Indirectly referencing the APU/CCD/GPU 7nm/6nm/5nm profile.

Ideal exampe of mixed => 7nm+ Zen3 / 7nm+ RDNA2 IP and 7nm I/O on 6nm for Cezanne. Since, Zen3/RDNA2's node is on a case by case basis.
 
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Veradun

Senior member
Jul 29, 2016
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No, you have it completely wrong. N6 is what N7+ should have been. Going from N7 or N7P to N7+, you need to rework your entire design and flow, which takes time and money. Going from N7 or N7P to N6 is a simple port.

N7+ is a dead end node that's more trouble than it's worth. If companies are going to go through the effort of creating a new design, they're going to N5/N5P, not N7+.
And this is why TSMC is fading out that naming scheme and calling everything N7 class
 

eek2121

Senior member
Aug 2, 2005
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So, yeah, this guy usually just throws a bunch of sh*t up against the wall just to see what sticks.
But, how are you 100% sure that there will be no Zen3+? Got a link, proof, other info?
Cut out with the personal attacks.

I don’t make redacted up, find something I’ve said that has been proven to be “wrong”. The person I replied to claimed there would be Zen 2+.

EDIT: Also, unlike some of you, I don’t live and die by these forums. I have a business to run.

We have a zero tolerance policy for profanity in the tech sub forums.

Iron Woode
Super Moderator
 
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coercitiv

Diamond Member
Jan 24, 2014
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EDIT: Also, unlike some of you, I don’t live and die by these forums. I have a business to run.
Well, after you're done running the business for today, come back and read again what Ajay wrote. You may be surprised and somewhat embarrassed.

The person I replied to claimed there would be Zen 2+.
The person you replied to was talking about Zen 3+.
 
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exquisitechar

Senior member
Apr 18, 2017
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Man, I wish we got some Zen 3 samples in the wild. Crazy how there hasn’t been a single one spotted yet.
Cut out with the personal attacks.

I don’t make redacted up, find something I’ve said that has been proven to be “wrong”. The person I replied to claimed there would be Zen 2+.

EDIT: Also, unlike some of you, I don’t live and die by these forums. I have a business to run.
He’s talking about Moore’s Law Is Dead, not you, lol.
 
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amrnuke

Senior member
Apr 24, 2019
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Cut out with the personal attacks.

I don’t make redacted up, find something I’ve said that has been proven to be “wrong”. The person I replied to claimed there would be Zen 2+.

EDIT: Also, unlike some of you, I don’t live and die by these forums. I have a business to run.
He was agreeing with you...
 
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amrnuke

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Apr 24, 2019
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No, you have it completely wrong. N6 is what N7+ should have been. Going from N7 or N7P to N7+, you need to rework your entire design and flow, which takes time and money. Going from N7 or N7P to N6 is a simple port.

N7+ is a dead end node that's more trouble than it's worth. If companies are going to go through the effort of creating a new design, they're going to N5/N5P, not N7+.
That being said, unless Zen4 is substantially a port of Zen3, then Zen3's node has little bearing on Zen4's node (which is clearly labeled as 5nm).

But since AMD are on N7 now with Zen2, it would be interesting to see what process they choose for Zen3, N6 is possible, I guess, considering it's "N7 class". Though if that's the case, I'm not sure why they labeled it "7nm" instead of "N7". Maybe that would have raised too many eyebrows. Wish we had some leaks!
 

Ajay

Diamond Member
Jan 8, 2001
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That became a common assumption after AMD's FAD where they stated that Milan is coming in "late 2020" whereas Zen 3 will hit the consumer market "later this year".
Thanks! I read elsewhere that it was later this year. But AT summed it up better
The company clarified that Zen 3 will hit the consumer market ‘later this year’, meaning late 2020.
Now I understand people's comments.
 
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Valantar

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Aug 26, 2014
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I think they summed it up wrong. :p ‘later this year’ != 'late this year' That can be, but is not necessarily the case.
When a business is talking about a release date in vague terms the best practice is to assume the very latest possible date within the time span given, as businesses talk in CYA language. Which is why "later this year" should be read as "before 2021 (up to and including Dec. 31st 2020)". If it were Q3 they would say Q3, as that would make investors happy and drive up stock prices. Now, December 31st is unlikely due to it missing holiday sales, but late November or early December for Zen 3 hitting stores? Wouldn't surprise me even slightly.
 

maddie

Diamond Member
Jul 18, 2010
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When a business is talking about a release date in vague terms the best practice is to assume the very latest possible date within the time span given, as businesses talk in CYA language. Which is why "later this year" should be read as "before 2021 (up to and including Dec. 31st 2020)". If it were Q3 they would say Q3, as that would make investors happy and drive up stock prices. Now, December 31st is unlikely due to it missing holiday sales, but late November or early December for Zen 3 hitting stores? Wouldn't surprise me even slightly.
Who in this present world situation will state a definite release date many months in advance? So much uncertainty exists.
 

Thunder 57

Golden Member
Aug 19, 2007
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When a business is talking about a release date in vague terms the best practice is to assume the very latest possible date within the time span given, as businesses talk in CYA language. Which is why "later this year" should be read as "before 2021 (up to and including Dec. 31st 2020)". If it were Q3 they would say Q3, as that would make investors happy and drive up stock prices. Now, December 31st is unlikely due to it missing holiday sales, but late November or early December for Zen 3 hitting stores? Wouldn't surprise me even slightly.
I always get a kick out of it when a company uses H1/H2 instead of Q2/Q4. We know what you're up to.
 

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