Predictions for Ryzen/EPYC nodes and products into 2021

[ksec]

10% is certainly doable, given how Intel has already shown what can be done and AMD learning from it.

And the time table seems very slow, and I think the main problem is GF, 7nm node.

I bet Zen 3 will be PCI-E 5.0 and DDR 5. My biggest concern is Memory Controller and PCI-E controller stability. I hope they take time to QA those very thoughtfully.

The roadmap for AMD is solid, and very practical. Compare to whatever Intel that is over promise and under deliver. Again my biggest concern is GF capacity. 7nm is already slower then 14nm due to more mask. AMD is in a very tough spot, I hope they get through.

 

[Yotsugi]

Again my biggest concern is GF capacity.

Why is this even a concern as long as TSMC exists?

 

[dacostafilipe]

However, dual-sourcing means producing mask sets at both GlobalFoundries and TSMC which is costly, time-consuming and labour-intensive.

Exactly, because of the costs, I don't see AMD producing the same CPU on both foundries.

For these reasons, I doubt there will be a 2-CCX die. The safe route for the 7nm transition is to stick to the current MCM formula, i.e. a single 3-CCX die across Ryzen, ThreadRipper and EPYC product lines.

If you play too safe, you risk loosing momentum. Just have a look at Intel.

 

[beginner99]

ow tables turned in just 3 short years. Back then in 2015 we had rumors of a "brand new core" and almost nobody in their right mind believed AMD had resources and money to go head to head with intel in high IPC high core count race. That is now a reality

The only reason it came this way is because intel already had delays and issues with 14nm and now mostly due to the 10 nm fiasco. Back in 2015 the plan was to have icelake out by now on 10 nm and not another skylake stepping 14 nm.

I wanted to add that from a risk perspective that AMD will certainly stay with a 2xccx die. 15% IPC + higher clocks is more than enough performance increase. Plus how would a 3xccx die work? If a ccx doesn't find the data in current ryzen it only has to look in one other CCX. With 3ccx it will increase latency as data could be in one or the other ccx or what am I missing?

 

[NostaSeronx]

Why is this even a concern as long as TSMC exists?

AMD has a WSA with GlobalFoundries. Which basically is fab with us or pay us if you don't for AMD.

The issue is most of GlobalFoundries customers have dropped 14nm/12nm/7nm products for 22FDX/12FDX. This has led to GloFo Malta management looking at going FDSOI as well. Only one customer is exclusive at GlobalFoundries and that is IBM. Even they might be shifting resources from 7LP to 12FDX. For reasons I am not talking about as it is a government issue.
//Malta defines the FDX nodes anyway, why not produce FDX as well. - Management.

Speculation: AMD is going to shift FinFET designs to TSMC. While producing FDSOI designs at GloFo Chengdu/Malta/Dresden. This split allows AMD to get full scale IoT to HPC coverage. Which Mubalada Technology wants and will get from AMD.

 

[CatMerc]

Its still a trade-off Intel could also have played - going wider is no mystery unknown to Intel - but they did not and it is save to assume Intel had reason for this. My argument was never related to the question how you achieve IPC - but going up from there is equally hard.
In you particular example this means, that being wider and increasing utilization is as hard as keeping high utilization and going wider - in the end you are facing the same problem.

I'm almost certain Ice Lake is going to be wider. So in a sense, Intel "did", it's just not leaving their labs because 10nm is screwed up.

The only reason it came this way is because intel already had delays and issues with 14nm and now mostly due to the 10 nm fiasco. Back in 2015 the plan was to have icelake out by now on 10 nm and not another skylake stepping 14 nm.

I wanted to add that from a risk perspective that AMD will certainly stay with a 2xccx die. 15% IPC + higher clocks is more than enough performance increase. Plus how would a 3xccx die work? If a ccx doesn't find the data in current ryzen it only has to look in one other CCX. With 3ccx it will increase latency as data could be in one or the other ccx or what am I missing?

The CCX's aren't directly connected, but rather they go through the Scalable Data Fabric.

https://en.wikichip.org/w/images/8/8f/amd_zeppelin_sdf_plane_block.svg

In a situation with an additional CCX, you'd just snoop two CCX's at the same time rather than one. There's no reason to do the snooping sequentially aside from potentially wasting power. (Which is done all the time for the sake of performance)

 

[Yotsugi]

Which basically is fab with us or pay us if you don't for AMD.

Then Lisa pays, fabs Rome at TSMC and boots Intel out of the datacenter.
It's that simple!
Time to market is of utmost importance right now, since Intel TMG is a clown fiesta.
And no, AMD won't touch FDSOI.
Its useless to them.
:^)

I'm almost certain Ice Lake is going to be wider.

Define 'wider'.
Front or back-end?

 

[moinmoin]

Thanks. I have been looking for info to corroborate that slide, but I have not found anything yet. It does make some sense though, as otherwise AMD's whole roadmap would be reliant on 7nm yield and capacity.

Like Raven Ridge Picasso is likely an in-between chip again, still using the old node (in this case 12nm) but making use of the necessity/opportunity of doing a new design to test run features planned for the next gen.

 

[ksec]

I remember Intel has challenged whether producing x86 CPU in TSMC would break the agreement with AMD. The settlements allows some sort of APU designed in TSMC. But I am not sure if AMD is truly free from GF in terms of x86.

WSA now has much more flexibility, and AMD actually paid for that flexibility in their recent earning. The problem is now GF isn't so sure of investing more into 7nm capacity, unlike TSMC which has lots of customers ready to fill in whatever they have left. GF doesn't have that luxury and relies literally on AMD only. The 7nm node IBM uses is different. So if GF invest and AMD cant sell as much as they projected, GF is screwed with no one to fill in, if they don't invest then AMD may one day move all to TSMC.

In a perfect world ( for GF ), Qualcomm would have fill the gap their their other Server offering. But it doesn't seems anyone is interested in GF offering. At least none of the high profile ones. So right now GF is doing what should be best for its business, concentrating on its pretty amazing FDSOI. Which seems to be picking up orders quite well.

I think in the next 2 - 3 years AMD or GF will have to meet and make the call to what is best for both of them. Unless Samsung decided to buy GF or AMD or help AMD to fab CPU.

Then Lisa pays, fabs Rome at TSMC and boots Intel out of the datacenter.
It's that simple!
Time to market is of utmost importance right now, since Intel TMG is a clown fiesta.
And no, AMD won't touch FDSOI.

AMD still doesn't have that many cash, and it is very resources constrained. Why Pay money and get nothing out of it?

EPYC has been available for nearly a year, has it booted Intel out of DC? It hasn't even moved the needle ( yet )

As a matter of fact, AMD needs more time to market its importance and alternative. It already has a better product out there.

I know it is the whole executive team's responsibility. But I cant name a CEO in big enterprise that has done a better job then Lisa in terms of product launch, market fit, and execution. ( Arguably Time Cook is still better, but he has all the resources he need or could use, compare to how little Lisa has / had )

 

[CatMerc]

Define 'wider'.
Front or back-end?

Both.

I remember Intel has challenged whether producing x86 CPU in TSMC would break the agreement with AMD. The settlements allows some sort of APU designed in TSMC. But I am not sure if AMD is truly free from GF in terms of x86.

WSA now has much more flexibility, and AMD actually paid for that flexibility in their recent earning. The problem is now GF isn't so sure of investing more into 7nm capacity, unlike TSMC which has lots of customers ready to fill in whatever they have left. GF doesn't have that luxury and relies literally on AMD only. The 7nm node IBM uses is different. So if GF invest and AMD cant sell as much as they projected, GF is screwed with no one to fill in, if they don't invest then AMD may one day move all to TSMC.

In a perfect world ( for GF ), Qualcomm would have fill the gap their their other Server offering. But it doesn't seems anyone is interested in GF offering. At least none of the high profile ones. So right now GF is doing what should be best for its business, concentrating on its pretty amazing FDSOI. Which seems to be picking up orders quite well.

GF has 60,000 wafer starts per month capacity at Fab 8, the one with 14nm and 7nm capacity. AMD only shipped 5 million Ryzen in a full year. That's half of what this fab can produce a month. And yet capacity is full?
It's safe to assume GF has undisclosed leading edge customers, and I wouldn't be surprised to see it again for 7nm.

Also, GF's 7nm isn't different. You have one 7nm with multiple standard cells to choose from, and two metalization stacks, allowing you to tune for performance, power, and density as needed. AMD has the same node as IBM, and as part of IBM's agreement with GloFo, GloFo will keep making such nodes.

 

[jpiniero]

IIRC the consoles are also being fabbed at GloFo now.

 

[Yotsugi]

IIRC the consoles are also being fabbed at GloFo now.

Consoles are still TSMC 16FF+, though.

 

[formulav8]

I'm almost certain Ice Lake is going to be wider. So in a sense, Intel "did", it's just not leaving their labs because 10nm is screwed up.

AMD said they had Ice lake in mind when they designed Zen 2. But looks like Zen 2 could be going up against a more Sky Lake variant instead of the full Ice Lake core. Should be quite interesting what Zen 2 brings.

 

[wahdangun]

AMD has a WSA with GlobalFoundries. Which basically is fab with us or pay us if you don't for AMD.

The issue is most of GlobalFoundries customers have dropped 14nm/12nm/7nm products for 22FDX/12FDX. This has led to GloFo Malta management looking at going FDSOI as well. Only one customer is exclusive at GlobalFoundries and that is IBM. Even they might be shifting resources from 7LP to 12FDX. For reasons I am not talking about as it is a government issue.
//Malta defines the FDX nodes anyway, why not produce FDX as well. - Management.

Speculation: AMD is going to shift FinFET designs to TSMC. While producing FDSOI designs at GloFo Chengdu/Malta/Dresden. This split allows AMD to get full scale IoT to HPC coverage. Which Mubalada Technology wants and will get from AMD.

Wasn't the WSA term if GF run out of capacity there would be no penalties?

 

[wahdangun]

Both.

GF has 60,000 wafer starts per month capacity at Fab 8, the one with 14nm and 7nm capacity. AMD only shipped 5 million Ryzen in a full year. That's half of what this fab can produce a month. And yet capacity is full?
It's safe to assume GF has undisclosed leading edge customers, and I wouldn't be surprised to see it again for 7nm.

Also, GF's 7nm isn't different. You have one 7nm with multiple standard cells to choose from, and two metalization stacks, allowing you to tune for performance, power, and density as needed. AMD has the same node as IBM, and as part of IBM's agreement with GloFo, GloFo will keep making such nodes.

But Polaris and Vega was produced in GF.

 

[NostaSeronx]

Wasn't the WSA term if GF run out of capacity there would be no penalties?

AMD pays if they do not fab at GloFo or under cut GlobalFoundries. GlobalFoundries pays if they do not give AMD the full committed wafer supply. AMD purchases at a lower cost through "competitive market pricing." GlobalFoundries can only pay for committed wafers they failed to provide called decommitted wafers. AMD however pays for all damages that they can cause to GlobalFoundries.

7LP is competitive price-wise against whoever is cheapest in 7nm FinFETs.
22FDX is competitive price-wise against whoever is cheapest in post-28nm "22nm" market. While providing an actual 22nm node; 14nm FDSOI(20nm FDSOI pre-2014), 22nm low BEOL(same as 22nm PDSOI), 28nm high BEOL(same as 28nm nodes).

The WSA amendment is specific to 14nm/7nm. While any node GlobalFoundries produce that isn't listed in the WSA amendment falls under the original WSA. Aka, don't fab 22FDX, gotta pay us. There is a reason why the stacked roadmap;
https://techreport.com/r.x/cpt-forum-13/glofo-roadmap.png
Under this roadmap AMD only had to purchase the highest performing node per generation. All below was waived as it is a single node roadmap with highest performing to lowest performing. (20LPM was superseded by 14LPE(78CPP+/9T) which AMD switched to then converted to 14LPP.
https://1.bp.blogspot.com/-WxBFl14W...530-h299-p-k/GlobalFoundries-14nm-Roadmap.png)

Became the dual-line roadmap;
https://i.imgur.com/hvgvQtJ.png
Under this roadmap AMD has to traverse both roads or pay GlobalFoundries. As it isn't a single node roadmap anymore, etc.

AMD had to buy 12LP, they also have to buy 22FDX and 12FDX, etc.

AMD pays per quarter for example:
-> Q1 2019;
Dresden: 80,000 wafers per month, so up to 240,000 22FDX priced wafers of damage.
Malta: 60,000 wafers per month, so up to 180,000 22FDX priced wafers of damage.
-> Qx 2020;
Chengdu: 65,000 wafers per month, so up to 195,000 22FDX priced wafers of damage.
Dresden* 110,000 wafers per month, so up to 336,000 22FDX priced wafers of damage.
Malta " " "

Micro-Ryzen/Micro-EPYC platform is desirable ->
http://www.eenewseurope.com/news/european-server-project-promotes-arm-fdsoi/page/0/3
^-- 32-core Cortex-A53
https://www.eetimes.com/document.asp?doc_id=1330129
^-- 48-core Cortex-A53

Getting an x86 design to compete is desirable for Euro-market.

 

[AtenRa]

This really makes sense.

Why would AMD try to add more cores on Ryzen instead of improving frequency and IPC?

So, I'm sticking with my two dies speculation:

• 2 CCX for Ryzen and possibly low core count TR/Epyc
• 3 CCX for TR/Epyc

I predict that ZEN 2 will be a 6core CCX and RYZEN 3xxx for AM4 socket will be 12 Core (2x 6core CCX)

So eventually some time next year we could have
RYZEN R3 3xxx = 6Core
RYZEN R5 3xxx = 8Core
RYZEN R7 3xxx = 10 and 12 Core

 

[Tuna-Fish]

Its still a trade-off Intel could also have played - going wider is no mystery unknown to Intel - but they did not and it is save to assume Intel had reason for this. My argument was never related to the question how you achieve IPC - but going up from there is equally hard.

No need to play "could have":s -- Intel also went wider with Skylake. My entire point is that AMD has a clearly mapped route to raise IPC. They know exactly what measures they need to do it, it just takes effort. The ways they can use to raise IPC are not the ones Intel used in Broadwell-Skylake-Caby lake iterations, as those are largely things AMD has already done. Rather, AMD can hunt skylake IPC by doing the things that Intel did in SNB->Haswell->Broadwell transition.

AMD has a WSA with GlobalFoundries. Which basically is fab with us or pay us if you don't for AMD.

The issue is most of GlobalFoundries customers have dropped 14nm/12nm/7nm products for 22FDX/12FDX. This has led to GloFo Malta management looking at going FDSOI as well. Only one customer is exclusive at GlobalFoundries and that is IBM. Even they might be shifting resources from 7LP to 12FDX. For reasons I am not talking about as it is a government issue.
//Malta defines the FDX nodes anyway, why not produce FDX as well. - Management.

Speculation: AMD is going to shift FinFET designs to TSMC. While producing FDSOI designs at GloFo Chengdu/Malta/Dresden. This split allows AMD to get full scale IoT to HPC coverage. Which Mubalada Technology wants and will get from AMD.

All of this is broadly false. Why do you act like you have some kind of sources, spouting supposed knowledge like you know something?

 

[beginner99]

So eventually some time next year we could have
RYZEN R3 3xxx = 6Core
RYZEN R5 3xxx = 8Core
RYZEN R7 3xxx = 10 and 12 Core

this makes sense as the 4 core part is covered by the APU and possibly an Athlon branded cpu-only based on the APU.

AFAIK in current Ryzen you need the same amount of cores active in each ccx. If they go with 3xccx with 4 cores, we would get a 12, 9, 6 core versions. the 9-core one being the odd man out. Also in you example they could raise prices for the top sku. They have established the brand by then. I'm sure they could sell a 12-core for $500 easily, 10-core at $400 and 8-core like now, but higher IPC and higher frequency.

 

[AtenRa]

this makes sense as the 4 core part is covered by the APU and possibly an Athlon branded cpu-only based on the APU.

AFAIK in current Ryzen you need the same amount of cores active in each ccx. If they go with 3xccx with 4 cores, we would get a 12, 9, 6 core versions. the 9-core one being the odd man out. Also in you example they could raise prices for the top sku. They have established the brand by then. I'm sure they could sell a 12-core for $500 easily, 10-core at $400 and 8-core like now, but higher IPC and higher frequency.

Personally Im expecting something like that,

R9 3800 and 3800X - 12 cores at $450 and $550
R7 3700 and 3700X - 10 cores at $330 and $399
R5 3600 and 3600X - 8 cores at 199$ and $249
R3 3500 and 3400 - 6 cores at $129 and $149

 

[jpiniero]

AFAIK in current Ryzen you need the same amount of cores active in each ccx. If they go with 3xccx with 4 cores, we would get a 12, 9, 6 core versions. the 9-core one being the odd man out.

You could still do 8, as that would be 2 CCX fully enabled with the other ccx(s) fully disabled.

 

[Topweasel]

The only reason it came this way is because intel already had delays and issues with 14nm and now mostly due to the 10 nm fiasco. Back in 2015 the plan was to have icelake out by now on 10 nm and not another skylake stepping 14 nm.

I wanted to add that from a risk perspective that AMD will certainly stay with a 2xccx die. 15% IPC + higher clocks is more than enough performance increase. Plus how would a 3xccx die work? If a ccx doesn't find the data in current ryzen it only has to look in one other CCX. With 3ccx it will increase latency as data could be in one or the other ccx or what am I missing?

A third CCX would have minimal affect on latency. All you need is an extra pathway between CCX's and they could be connected in a ring. The biggest issue is that right now each CCX has it's own DRAM controller pathed to it. So you could keep the same memory latency by going 3 channel memory. But I doubt they would do that I have a feeling Zen 3 is going to be more than a Zen 2+ but probably more on a arch level and that on a configuration level it will be closer to Zen 2.

 

[CatMerc]

A third CCX would have minimal affect on latency. All you need is an extra pathway between CCX's and they could be connected in a ring. The biggest issue is that right now each CCX has it's own DRAM controller pathed to it. So you could keep the same memory latency by going 3 channel memory. But I doubt they would do that I have a feeling Zen 3 is going to be more than a Zen 2+ but probably more on a arch level and that on a configuration level it will be closer to Zen 2.

Nope, there is no direct connection between the two CCX's, and neither do they each have their own memory controller. The memory controller and CCX's all connect to the Scalable Data Fabric from which everything is routed. So it's pretty much just a matter of adding another path way for the third CCX's to the SDF, and beefing up the bandwidth to feed more cores, neither of which will be a problem.

 

[wahdangun]

No need to play "could have":s -- Intel also went wider with Skylake. My entire point is that AMD has a clearly mapped route to raise IPC. They know exactly what measures they need to do it, it just takes effort. The ways they can use to raise IPC are not the ones Intel used in Broadwell-Skylake-Caby lake iterations, as those are largely things AMD has already done. Rather, AMD can hunt skylake IPC by doing the things that Intel did in SNB->Haswell->Broadwell transition.



All of this is broadly false. Why do you act like you have some kind of sources, spouting supposed knowledge like you know something?

So you are saying, what AMD need to do is increasing utilization ? Because right now they are as wide as Skylake ? Yeah make sense since their smt gain is higher than intel.

 

[Topweasel]

Nope, there is no direct connection between the two CCX's, and neither do they each have their own memory controller. The memory controller and CCX's all connect to the Scalable Data Fabric from which everything is routed. So it's pretty much just a matter of adding another path way for the third CCX's to the SDF, and beefing up the bandwidth to feed more cores, neither of which will be a problem.

That's the Path I am talking about. I get how IF and their other interlinks work. Point being the the DRAM controllers are on opposite ends of the CPU design and have interconnects to the nearest CCX. Obviously if they can handle whole dies with inactive memory controllers they can handle a CCX not having direct access to the memory controller. Just saying that it would affect memory latency to that CCX. Where as in a 3 CCX ring, latency between CCX's wouldn't really be affected greatly as the complexity wouldn't be that high and its still the same distance/trip between the one CCX and another. Whereas if they have 4 CCX units they would need to go back to more of a matrix/mesh design (increased complexity) or use a ring design but require that a CCX will always have increased latency to one of the other 3.