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Predictions for Ryzen/EPYC nodes and products into 2021

Bondrewd

Senior member
Oct 16, 2017
498
43
76
#76
Point being the the DRAM controllers are on opposite ends of the CPU design and have interconnects to the nearest CCX.
They don't.
And there's only one, dual-channel DRAM controller on Zeppelin.
WikiChip has a Zeppelin diagram.
Go look at it or something.
 

NostaSeronx

Platinum Member
Sep 18, 2011
2,188
9
106
#77
@Topweasel
They don't.
And there's only one, dual-channel DRAM controller on Zeppelin.
WikiChip has a Zeppelin diagram.
Go look at it or something.
https://en.wikichip.org/wiki/amd/microarchitectures/zen#Memory_Controller
https://en.wikichip.org/wiki/amd/microarchitectures/zen#Zeppelin
https://en.wikichip.org/wiki/amd/microarchitectures/zen#APU

Specifically, these ones that are labeled.
---
@Tuna-Fish AMD agreed to do "Advanced FDSOI" in 2011, btw. So, most of the problems from AMD not going GlobalFoundries is unfound.

Current GlobalFoundries plans.
Dresden => First GlobalFoundries GigaFab
Chengdu => Second GlobalFoundries GigaFab
Abu Dhabi => Third GlobalFoundries GigaFab
Malta => Fourth unless they start producing 22FDX/12FDX, in which case if they do they are second GigaFab.

Again, an unfound issue. As Malta has agreed to do 22FDX when TSMC/Intel does 22ULP/22FFL.
 
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Thunder 57

Senior member
Aug 19, 2007
563
7
116
#78
@Topweasel
https://en.wikichip.org/wiki/amd/microarchitectures/zen#Memory_Controller
https://en.wikichip.org/wiki/amd/microarchitectures/zen#Zeppelin
https://en.wikichip.org/wiki/amd/microarchitectures/zen#APU

Specifically, these ones that are labeled.
---
@Tuna-Fish AMD agreed to do "Advanced FDSOI" in 2011, btw. So, most of the problems from AMD not going GlobalFoundries is unfound.

Current GlobalFoundries plans.
Dresden => First GlobalFoundries GigaFab
Chengdu => Second GlobalFoundries GigaFab
Abu Dhabi => Third GlobalFoundries GigaFab
Malta => Fourth unless they start producing 22FDX/12FDX, in which case if they do they are second GigaFab.

Again, an unfound issue. As Malta has agreed to do 22FDX when TSMC/Intel does 22ULP/22FFL.
Do you have any sources regarding this?
 

Topweasel

Diamond Member
Oct 19, 2000
4,500
94
126
#79
They don't.
And there's only one, dual-channel DRAM controller on Zeppelin.
WikiChip has a Zeppelin diagram.
Go look at it or something.
Probably a good idea to fact before you jump down someone's throat. There are certainly two dram controllers on opposite ends of the die position right next to their respective ccx's.
 

NostaSeronx

Platinum Member
Sep 18, 2011
2,188
9
106
#80
Probably a good idea to fact before you jump down someone's throat. There are certainly two dram controllers on opposite ends of the die position right next to their respective ccx's.
Those are the IFIS... technically they can be used for Gen-Z DRAM. Except, the MCT doesn't connect to either. The MCT is above/around the unconnected IFOP next to the two DDR4 phys. (Yes, there is a second one to the right of the first. The DCT is however shared.)
300px-amd_zeppelin_basic_block.svg.png

950px-amd_zen_octa-core_die_shot.png

600px-amd_zeppelin_basic_block_4-dies.svg.png


Do you have any sources regarding this?
I do, but I am not posting them. As they are easily found with an e-search.
 
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Topweasel

Diamond Member
Oct 19, 2000
4,500
94
126
#82
Those are the IFIS... technically they can be used for Gen-Z DRAM. Except, the MCT doesn't connect to either. The MCT is above/around the unconnected IFOP next to the two DDR4 phys. (Yes, there is a second one to the right of the first. The DCT is however shared.)
300px-amd_zeppelin_basic_block.svg.png

950px-amd_zen_octa-core_die_shot.png

600px-amd_zeppelin_basic_block_4-dies.svg.png


I do, but I am not posting them. As they are easily found with an e-search.
I found more images labeling 2 separate unconnected controllers. Not saying you are wrong but just saying there is good cause for the confusion.
 

Bondrewd

Senior member
Oct 16, 2017
498
43
76
#83
I found more images labeling 2 separate unconnected controllers. Not saying you are wrong but just saying there is good cause for the confusion.
These are old, and David's article has diagrams based on the actual ISSCC presentation on Zeppelin.
 

Topweasel

Diamond Member
Oct 19, 2000
4,500
94
126
#84
These are old, and David's article has diagrams based on the actual ISSCC presentation on Zeppelin.
I'll take your word for that. I don't track every detail as it comes out. Still didn't deserve being treated like I am silly for thinking so. Try being a little less obnoxious when correcting someone next time.
 

Topweasel

Diamond Member
Oct 19, 2000
4,500
94
126
#86
Literally never.
:^)
Also yes, do check WikiChip regularly for anything semicon.
I do every once and a while. But I am not re-reading the same page over and over again just to see if anything changed every month. This isn't a "check google" before posting issue. Many sites referenced the separated Dram controllers. I double checked to see if my memory served me right before posting. If you have updated information regarding something then just say so and link the new info. Doesn't have to be accusatory.
 

moinmoin

Senior member
Jun 1, 2017
566
20
96
#87
I do every once and a while. But I am not re-reading the same page over and over again just to see if anything changed every month. This isn't a "check google" before posting issue. Many sites referenced the separated Dram controllers. I double checked to see if my memory served me right before posting. If you have updated information regarding something then just say so and link the new info. Doesn't have to be accusatory.
Just for the record, following annotated Zeppelin die shot still in use was added back on April 4th last year:
iPRCiHa.png


Whenever talking about IF/SDF/SCF I also regularly like to refer to/include following flow chart:
E3UnkU3.png
 

Olikan

Golden Member
Sep 23, 2011
1,881
3
91
#90
I am more confused bcause only the central half CUs have acess to the chiplet L2 cache

Anyway, i just wanted to show that cpu on interposer is in works
 
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Vattila

Senior member
Oct 22, 2004
362
50
136
#91
Cpu and Gpu chiplets on an interposer
Note that only a single CPU chiplet (CCX) is drawn in that diagram. Here is my version with 4 CCXs. Also, due to the similarity of the top and bottom half, i.e. being replicas of each other, I have separated them into two interposers, for a more modular design, interconnected using on-package Infinity Fabric (as in current EPYC and ThreadRipper packaging, but perhaps optimized in EMIB-style). I have also put the DRAM (4 stacks of HBM) onto the interposer. Further I suppose that a CCX would make a too small chiplet to be practical, so I assume the CCXs are on a single die, with additional SoC logic (un-core).

9114301_5d950df06ef0d982f70c8a21c6805db5.png

PS. If you split this design vertically, you can build it from even smaller components, i.e. a Raven Ridge-like module consisting of 1 CCX, 1 GPU and 2 stacks of HBM.​
 
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Jul 21, 2000
14,378
0
81
#92
I think AMD is going to slowly chip away at Intel's lead and marketshare over time. Intel has been stagnant for a long time now and AMD has shown they are good at refining their products and extracting more performance from them. Clockspeed is really the only advantage Intel has left. I really hope AMD can hit 4.5ghz with their upcoming chips in the next year.
 

Spartak

Senior member
Jul 4, 2015
203
30
86
#93
To me it seems very unlikely AMD will upgrade the CCX to six cores for Zen2. Power envelope for (ultra)mobile is so critical even at 7nm you wouldnt get high enough clocks alongside those extra cores. And that extra silicon is expensive as well. Having two CCX designs for desktop/server and mobile seems to go against the modular design principle where every product is based on that same CCX but in a different package.

A 3xCCX desktop/server and maybe a 2xCCX/1xGPU as a budget desktop option seems likely to me for Zen2. Mobile and SFF PC will stay at 1xCCX/1xGPU.

For Zen3 on 5nm I can see them moving to a 6 core CCX, ideally that would be in 2021.

Me personally, the 2400G feels snappy enough for the coming years. I'll probably upgrade when they move to 6 cores for the APU and hit 5ghz on turbo, in a 45/65W power budget. With the additional extra IPC that would roughly double the performance. But 2021 seems awfully optimistic for that, I'd say 2022/2023 seems more likely.
 
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moinmoin

Senior member
Jun 1, 2017
566
20
96
#94
Don't think this is worth a new thread so resurrecting this one.

The Ryzen chipsets so far helped indicate the start of the respective Ryzen gen.
X370 for Ryzen 1xxx arrived in February 2017
X470 for Ryzen 2xxx arrived in April 2018

A Taiwanese forum leak now suggest X570 will launch at Computex which goes from May 28th to June 1st 2019. While later than expected this would be in line of the 14 months rhythm so far.

n7hKrRi.png
 

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