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Predictions for Ryzen/EPYC nodes and products into 2021

Thala

Senior member
Nov 12, 2014
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#26
Of course, there are no guarantees but precisely because Zen is a new design, I would expect version 2 to show a decent increase as they should have lots of low-hanging fruit.
My argument is rather, that Zen is already at Broadwell IPC level - so if there were low hanging fruits left Intel would have used them already with Broadwell->Skylake->Cabylake interations.
 
Dec 29, 2015
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#27
My argument is rather, that Zen is already at Broadwell IPC level - so if there were low hanging fruits left Intel would have used them already with Broadwell->Skylake->Cabylake interations.
So... Since AMD's Zen was not affected by Speculative Execution Side Channel Vulnerability, Intel could not have been affected either? They are two different micro-architectures from two different companies...
 

moinmoin

Senior member
Jun 1, 2017
566
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#28
My argument is rather, that Zen is already at Broadwell IPC level - so if there were low hanging fruits left Intel would have used them already with Broadwell->Skylake->Cabylake interations.
Why would AMD's new Zen design care what level of Intel's Core design it is at IPC wise? Intel picked up the low hanging fruits after the first gen that was Nehalem. AMD will do the same with Zen 2. All you are arguing for is that Intel is overdue with a new core design, not that there is some fictitious IPC wall as you might think.
 

Thala

Senior member
Nov 12, 2014
598
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#29
Why would AMD's new Zen design care what level of Intel's Core design it is at IPC wise? Intel picked up the low hanging fruits after the first gen that was Nehalem. AMD will do the same with Zen 2. All you are arguing for is that Intel is overdue with a new core design, not that there is some fictitious IPC wall as you might think.
Oh - i am indeed arguing that there is a certain IPC wall which can be achieved with reasonable area and power resources - given that both are essentially architectures based on x64 ISA. I do _not_ argue that Intel needs an all new core architecture.
 

Thala

Senior member
Nov 12, 2014
598
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#30
So... Since AMD's Zen was not affected by Speculative Execution Side Channel Vulnerability, Intel could not have been affected either? They are two different micro-architectures from two different companies...
Being affected by Meltdown is an oversight and we would not see any CPU affected by Meltdown today if the issue would have been on the radar before - part of the reason is, that it is easy to fix. Regarding variations of Spectre - AMD is also affected.
 

IEC

Super Moderator
Super Moderator
Jun 10, 2004
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#31
Being affected by Meltdown is an oversight and we would not see any CPU affected by Meltdown today if the issue would have been on the radar before - part of the reason is, that it is easy to fix. Regarding variations of Spectre - AMD is also affected.
The following are with Meltdown/Spectre patches applied and enabled on Xeon v3/v4/Skylake Scalable as of June 2018. This is before the new round of Spectre v3a/v4 (NG) patches are out which will come with additional 2-8% penalties per Intel:

<redacted> on XenApp: 14-41% CPU utilization impact
<redacted> on Windows client OSes on Horizon VDI: 31%+ increase in CPU util and significant response time impact even after adding additional hardware
<redacted> on Horizon RDSH: 33%+ increase in CPU util and significant response time impact even after adding additional hardware

Skylake Xeons (Scalable series) shows the least impacts at 8-17% depending on workload while v3 and v4 Xeons can have over 40% CPU util impact and >70% response time impact in the worst case for <redacted>.

Needless to say, a lot of orgs in this sector have chosen to disable IBRS/Variant 2 remediation via Windows registry until they can get additional hardware in place. It's the most costly one performance-wise.

The main competitor's hardware doesn't take this kind of hit... I'd predict things are looking up for them. Especially with 48/64 core Epyc 2 on the way.
 

beginner99

Diamond Member
Jun 2, 2009
3,881
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#32
PCI-E Gen 4 is backwards compatible with PCI-E Gen 3, so slotting it into the existing AM4 motherboards will not be a problem. It will just work at Gen 3 speeds.
I doubt that will happen. Easier to just leave it as is with PCIe 3. Rumor says PCIe4 will be skipped in consumer segment as the need is limited. In fact the only need for faster PCIe for consumers is the chipset-CPU link (albeit CPU manufacturers could also uses 8 instead of just 4 lanes...).
 

CatMerc

Golden Member
Jul 16, 2016
1,105
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#33
Oh - i am indeed arguing that there is a certain IPC wall which can be achieved with reasonable area and power resources - given that both are essentially architectures based on x64 ISA. I do _not_ argue that Intel needs an all new core architecture.
You said it yourself, reasonable area and power resources. AMD will have a node three times the density :p
 

Thala

Senior member
Nov 12, 2014
598
1
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#34
You said it yourself, reasonable area and power resources. AMD will have a node three times the density :p
I doubt they going into gate-count linear to density gain - this would not be reasonable when looking at leakage alone. The question obviously is how much power/area loss are you willing to take to gain 15% performance. And since i do not believe the "low hanging fruits"-theory - i am skeptical about 15% IPC gain. And while for a desktop part not overly important they need to keep efficiency under control otherwise your are blowing the huge power savings of the 7nm node right out of the window.
 
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jpiniero

Diamond Member
Oct 1, 2010
5,805
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#35
I doubt that will happen. Easier to just leave it as is with PCIe 3. Rumor says PCIe4 will be skipped in consumer segment as the need is limited. In fact the only need for faster PCIe for consumers is the chipset-CPU link (albeit CPU manufacturers could also uses 8 instead of just 4 lanes...).
Since it's the same die, you may as well offer it.
 

CatMerc

Golden Member
Jul 16, 2016
1,105
6
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#36
I doubt they going into gate-count linear to density gain - this would not be reasonable when looking at leakage alone. The question obviously is how much power/area loss are you willing to take to gain 15% performance. And since i do not believe the "low hanging fruits"-theory - i am skeptical about 15% IPC gain. And while for a desktop part not overly important they need to keep efficiency under control otherwise your are blowing the huge power savings of the 7nm node right out of the window.
Right. As I said, it's the weakest part of my prediction since it's based purely on gut feeling. We'll see soon enough.
 
Feb 2, 2009
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#37
ZEN 2 at 7nm could have ~10% higher IPC + ~20% higher Fmax. So imagine an 8core Ryzen 3xxx with ST at 4.6GHz + 10% higher IPC vs current Ryzen 2xxx 65W TDP at ~200 USD.
 

Gideon

Senior member
Nov 27, 2007
413
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#38
10% Higher overall IPC seems doable. I'm hoping they manage more in AVX workloads e.g. 15%-20%
 

CatMerc

Golden Member
Jul 16, 2016
1,105
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#39
10% Higher overall IPC seems doable. I'm hoping they manage more in AVX workloads e.g. 15%-20%
My 15% number did assume they'd get wider vector units for AVX256.
 

Tuna-Fish

Senior member
Mar 4, 2011
904
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#40
My argument is rather, that Zen is already at Broadwell IPC level - so if there were low hanging fruits left Intel would have used them already with Broadwell->Skylake->Cabylake interations.
Zen achieves that IPC in a very different manner than Broadwell. In general, Zen is wider but has lower utilization. If Zen utilization was improved to Broadwell levels, it's IPC would be nearing Skylake. (At least in non-avx loads).
 

NeoLuxembourg

Senior member
Oct 10, 2013
663
0
106
#41
ZEN 2 at 7nm could have ~10% higher IPC + ~20% higher Fmax. So imagine an 8core Ryzen 3xxx with ST at 4.6GHz + 10% higher IPC vs current Ryzen 2xxx 65W TDP at ~200 USD.
This really makes sense.

Why would AMD try to add more cores on Ryzen instead of improving frequency and IPC?

So, I'm sticking with my two dies speculation:
  • 2 CCX for Ryzen and possibly low core count TR/Epyc
  • 3 CCX for TR/Epyc
 

CatMerc

Golden Member
Jul 16, 2016
1,105
6
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#42
This really makes sense.

Why would AMD try to add more cores on Ryzen instead of improving frequency and IPC?

So, I'm sticking with my two dies speculation:
  • 2 CCX for Ryzen and possibly low core count TR/Epyc
  • 3 CCX for TR/Epyc
If they expect volume high enough to split server and consumer dies then it makes sense. If they don't then then it's better to die harvest from the same die.
 

jpiniero

Diamond Member
Oct 1, 2010
5,805
42
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#43
This really makes sense.
Why would AMD try to add more cores on Ryzen instead of improving frequency and IPC?
Marketing reasons. But I do think there is a good chance Ryzen still tops out at 8 cores at least initially to maximize yield and anything more than that per die would be given to Epyc or Threadripper.
 

Thala

Senior member
Nov 12, 2014
598
1
106
#44
Zen achieves that IPC in a very different manner than Broadwell. In general, Zen is wider but has lower utilization. If Zen utilization was improved to Broadwell levels, it's IPC would be nearing Skylake. (At least in non-avx loads).
Its still a trade-off Intel could also have played - going wider is no mystery unknown to Intel - but they did not and it is save to assume Intel had reason for this. My argument was never related to the question how you achieve IPC - but going up from there is equally hard.
In you particular example this means, that being wider and increasing utilization is as hard as keeping high utilization and going wider - in the end you are facing the same problem.
 

inf64

Platinum Member
Mar 11, 2011
2,805
9
136
crazyworldofchips.blogspot.com
#45
I think ~15% "general" IPC improvement is reasonable to expect. If they beef up AVX2 execution potential to 2x256bit AVX2 ops per cycle per core then it means that load/store capability is also doubled which would be great. Finally Zen2 core might exceed Skylake IPC , excluding AVX512 cases of course. We'll have to wait and see but on HEDT and server AMD looks to be poised to overtake intel with 3rd iteration of Zen. How tables turned in just 3 short years. Back then in 2015 we had rumors of a "brand new core" and almost nobody in their right mind believed AMD had resources and money to go head to head with intel in high IPC high core count race. That is now a reality :).
 

Vattila

Senior member
Oct 22, 2004
362
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#46
So, I'm sticking with my two dies speculation
I am pretty convinced by now — after GlobalFoundries' CTO Gary Patton stated that they have aligned certain 7LP process features with TSMC's process, and that AMD needs more capacity than GlobalFoundries can offer — that AMD has a dual-source strategy in place to mitigate the immense risk they have taken on by betting so much of their roadmap on the 7nm process leap, as well as ensuring that they have the capacity to meet their targets on market share.

However, dual-sourcing means producing mask sets at both GlobalFoundries and TSMC which is costly, time-consuming and labour-intensive. To keep risk in check, I think they will be careful to not overextend.

For these reasons, I doubt there will be a 2-CCX die. The safe route for the 7nm transition is to stick to the current MCM formula, i.e. a single 3-CCX die across Ryzen, ThreadRipper and EPYC product lines.

Also note that the 12nm Ryzen 2000 series will probably live concurrently with the 7nm 3000 series for quite some time. Its 2-CCX "Zeppelin" die will be cheaper to produce, until 7nm yield and capacity fully supplants 12nm.

So, I suspect the plan is to produce the 3-CCX "Starship" die at GlobalFoundries, with TSMC as a source for additional volume beyond GlobalFoundries' capacity, as well as serving as a backup source, if GlobalFoundries' 7LP process should falter.

An interesting question is whether AMD will also dual-source the APU. It can be argued that it makes as much, if not more, sense from a perspective of volume. That said, I would not be completely surprised, considering limited 7nm volume and risk factors, as well as hints on leaked roadmaps (see below), if the next generation APU turns out to be just a refinement of Raven Ridge on 12nm.

amd-leaked-roadmap.jpg
 
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jpiniero

Diamond Member
Oct 1, 2010
5,805
42
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#49
Thanks. Do you have a source?

PS. Corrected typo "14nm" to "12nm" in my previous post.
That chart. It says "Raven Ridge architecture" implying it's not Zen 2.
 

Vattila

Senior member
Oct 22, 2004
362
50
136
#50
That chart. It says "Raven Ridge architecture" implying it's not Zen 2.
Thanks. I have been looking for info to corroborate that slide, but I have not found anything yet. It does make some sense though, as otherwise AMD's whole roadmap would be reliant on 7nm yield and capacity.
 

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