• Hey there Guest! This holiday season you have a chance to win some cool AnandTech swag! Check out “The Holiday Hotlist” giveaway, which you can find here.

Predictions for Ryzen/EPYC nodes and products into 2021

CatMerc

Golden Member
Jul 16, 2016
1,105
6
106
#1
I've been thinking about how Zen, Zen+, Zen 2, and Zen 3, all relate to each other. A leaked slide from AMD points to AMD taking a sort of tick tock approach, only naming it "inflection" and "optimization". This has been semi-confirmed by James Prior mentioning it. According to this cadence, we should see a Zen 2 optimization cycle after Zen 2, however AMD's own architecture and server roadmaps point to Zen 3 coming somewhere in 2020, where you would expect the Zen 2 optimization cycle to exist. So what gives? And there's also the question of manufacturing, where and what products will be made at TSMC's 7nm, and GloFo's 7nm, with Lisa Su claiming both will be used (but never detailed to what capacity).

Well, there's another interesting point to think about. We're at an "inflection" point in terms of the I/O technologies being offered. PCI-E Gen 4 is almost surely going to happen with EPYC 2, but PCI-E Gen 5 is being released very soon, offering yet another doubling of bandwidth over PCI-E Gen 4. And then we've got DDR5, with test IP already hitting JEDEC spec, and with JEDEC claiming the first products using DDR5 should hit the market somewhere in 2020.

This is all speculation based on probable rumors and my analysis!!!

Here's how I see things going:
- H2 2018: we're going to see Zen 2 based EPYC sampling to partners, manufactured on TSMC's 7nm. This is public information, with Lisa Su claiming they will use whichever fab is first ready, and TSMC is known to already be in HVM. AMD already has silicon back in the labs going through bring up, and Lisa held an EPYC 2 package at Computex.

- H1 2019: Launch of EPYC 2. This will be a sort of soft launch like EPYC 1 had, with just the specifications released, and some limited customer announcements. The actual ramp will happen later. EPYC 2 will have PCI-E Gen 4 support, and will have 48 cores as ServeTheHome claims.

- Q2 2019: Zen 2 Ryzen processors harvested from the same TSMC 7nm die will release. GloFo is not ready yet (they're only entering risk late 2018 at best), and yields of a fresh process like 7nm means there will be plenty of defective dies that could be sold to consumers. AMD is clearly trying to hit a yearly cadence of new processors to consumers, so this would be perfect timing. PCI-E Gen 4 is backwards compatible with PCI-E Gen 3, so slotting it into the existing AM4 motherboards will not be a problem. It will just work at Gen 3 speeds.
I'd expect these processors to clock in the 4.5-4.6GHz boost range and have ~15% higher IPC. Clockspeed estimate is based on ARM's claims of minor performance improvement with 7nm (on top of minor improvement of 10nm), along with a more complex Zen 2 design dropping clockspeeds a bit. Top mainstream will be 12 cores.

- Q4 2019: Ramp of EPYC 2. Since EPYC 2 sits on the same platform as EPYC 1, and its an advancement of an existing architecture, it will have a shorter certification cycle. In a Tech Analysts podcast, Patrick Moorhead claimed about 3-6 months faster is his estimate.

- H1 2020: Sampling of Zen 3 based EPYC 3 (Milan). AMD reportedly wants to be first to DDR5. AMD also prides themselves on their massive I/O capabilities with EPYC. Therefore I expect Zen 3 to have a DDR5 memory controller, along with PCI-E Gen 5, both of which should see the first devices in 2020. I also predict Zen 3 to use AMD's recently filed patents (forgot to save them, doh) which describe silicon bridges akin to Intel's EMIB, therefore reducing die to die latency and boosting bandwidth and power efficiency. All of this will be made on TSMC's 7FF+, allowing AMD to fit 16 cores per die with minimal die size expansion, enabling an EPYC of up to 64 cores according to both ServeTheHome, and CanardPC who initially broke the 64 Core/256MB L3 cache rumor.

- H1 2020: We will see AMD transition Ryzen to GloFo's 7nm, which should actually be ready by then. Due to the way the WSA works, this will increase margins for Ryzen based processors. In addition to that, if GloFo's performance claims hold, then GloFo's process should outperform TSMC's process. This would allow AMD to create an optimization cycle of Zen 2 for consumer with higher clockspeeds. I'd expect 4.8GHz-5GHz boost clocks, with maybe a minor 1%-2% IPC gain like Zen+. Still 12c max just as before.

- H2 2020: Launch of Zen 3 EPYC, fulfilling the 2020 promise.

- H1 2021: The release of AM5 socket, officially ending backwards compatibility with the AM4 socket. The AM5 socket will support PCI-E Gen 5, and DDR5. The new Ryzen lineup will be Zen 3 based, either made on 7FF+ or transitioned to GloFo's 7nm Gen 3 process. 7FF+ only promises efficiency and density improvements, while 7nm Gen 3 promises performance improvements too, so it would make sense to transition Zen 3 to it if the economics allow it.
I don't expect core counts to rise, but rather mainstream will maintain 12 cores at smaller die sizes and higher IPC/clockspeed.

-H2 2021: Ramp of Zen 3 EPYC


And that's it. After considering the economic viability, competitive landscape, and market opportunities of AMD, combined with AMD's own statements and probable leaks (probable sources only), I believe this is AMD's plan right now.
 
Last edited:

CHADBOGA

Golden Member
Mar 31, 2009
1,757
13
126
#2
- Q2 2019: Zen 2 Ryzen processors ..
I'd expect these processors to clock in the 4.5-4.6GHz boost range and have ~15% higher IPC.
I seriously doubt that. o_O
 

Jan Olšan

Senior member
Jan 12, 2017
255
4
76
#3
TSMC for Epyc 2 is not confirmed in any way. Forrest Norrod explicitly said that they are not revealing who makes it.

IMHO, there is still way too much riding on AMD's need to fulfil WSA order requerements and at the same time AMD also still has to stick to the arrangement where Epyc and Ryzen is just a single die - due to lack of RD/staff resources and the additional costs of making a second chip. I'd say that is actually their policy and they won't abandon it that soon.

Therefore, they virtually have to make Zen 2 CPU on GlobalFoundries. It is likely that they are willing to delay Zen 2 to wait for GloFo rather than jumping over to TSMC for the chip. Note that even if they used just TSMC for the Epyc/Ryzen CPU die, APU version would at least have to be on GloFo to cover at least part of WSA requirement. And that means you would still have doubled development efforts and costs on Zen 2. For these reasons, I'm not going to believe the TSMC conjectures until there is a solid proof.

I also doubt PCIe 5.0 will come that soon after 4.0. Gut feeling tells me that it won't appear on the first AM5 generation.
 

CatMerc

Golden Member
Jul 16, 2016
1,105
6
106
#4
I seriously doubt that. o_O
Zen is a fresh architecture. No doubt AMD has low hanging fruits they intend to pluck with Zen 2.

Remember that 7nm is a LOT more dense, they can increase complexity quite a bit without inflating core size. My clockspeed estimate takes into account the design complexity rising for the sake of IPC.

Admittedly its the weakest part of my predictions, there's just nothing to work with other than gut feeling. I will say that Skylake is not the end all be all, Intel hasn't hit an IPC wall, its just 10nm delaying all of their architectures. It won't be the benchmark to hit soon enough.

TSMC for Epyc 2 is not confirmed in any way. Forrest Norrod explicitly said that they are not revealing who makes it.

IMHO, there is still way too much riding on AMD's need to fulfil WSA order requerements and at the same time AMD also still has to stick to the arrangement where Epyc and Ryzen is just a single die - due to lack of RD/staff resources and the additional costs of making a second chip. I'd say that is actually their policy and they won't abandon it that soon.

Therefore, they virtually have to make Zen 2 CPU on GlobalFoundries. It is likely that they are willing to delay Zen 2 to wait for GloFo rather than jumping over to TSMC for the chip. Note that even if they used just TSMC for the Epyc/Ryzen CPU die, APU version would at least have to be on GloFo to cover at least part of WSA requirement. And that means you would still have doubled development efforts and costs on Zen 2. For these reasons, I'm not going to believe the TSMC conjectures until there is a solid proof.

I also doubt PCIe 5.0 will come that soon after 4.0. Gut feeling tells me that it won't appear on the first AM5 generation.
TSMC is the only one with any sort of production of 7nm. GloFo hasn't even reached risk or even completed the PDK. How do you think AMD already has samples in the lab?
EPYC 2 is 100% TSMC, nothing else makes sense.

They aren't willing to delay a thing, they paid a major charge to GloFo to be able to do this. EPYC 2 needs to come out as soon as possible to capitalize on Intel's 10nm delays. And since this will likely create a lot of unusable dies for EPYC, they'll most likely release it in consumer form too.

TSMC and GloFo 7nm are intentionally very similar to allow AMD to transfer their designs easily. I do expect the APU's to be made at GloFo, as their release timing makes sense to be manufactured there.

PCI-E 5 is officially coming much sooner than PCI-E 4 was to PCI-E 3. Its been known for a long time. Google PCI-E 5.
 
Last edited:

NeoLuxembourg

Senior member
Oct 10, 2013
663
0
106
#5
I like the general idea, but I have a question: Are we certain that AMD will continue the same "One die to rule them all" concept?

Speculation : What if they release a 3 CCX die AND a 2 CCX die, both on 7nm? With two foundries, we could even see the 3 CCX version at TSMC and a 2 CCX at GF at a latter
 
Mar 11, 2004
17,409
56
126
#6
Random crazy speculation, at Zen 3, we see a divergence. Consumer Zen goes all APUs. They keep the same pin setup as AM4, and the CPUs can operate in limited mode on older boards, and older CPUs can be used in newer ones, but to fully utilize what it offers you have to have newer a newer board (because they're built to a higher spec), but they call it AM5, to signal several things (PCIe 5, DDR5 support). I believe DDR5 has same pin layout as DDR4, so AM5 has support for both (maybe they show off systems with a mix, and they make it so you have graphics prioritize the DDR5; so you could boost your graphics by getting some DDR5 but using some DDR4 you already have, making the DDR5 more affordable).

I think GPUs will be heavily valued, so I could see them top at even 8c/16t with the GPU getting the preference over adding CPU cores. Intel certainly is (and Apple has been for some time). AMD should be quite competitive on the CPU side, so they'd be stupid to let their GPU advantage languish. On this front, I think Zen 2 will split some, in that we'll see a 12c/24t top chip ($399 or maybe $449 with a 10c/20t one at $399, or they go $429/379), and then lower than that will be all APUs, and that things will be segmented quite a bit; have a top 8c/16t APU with quad channel at $349, a 6c/12t quad channel at $299, then 6c/12t with 3 channels - one dedicated for graphics alone - at $249, 4c/8t with 3 channels at $199, and then 4c/8t with dual channel at $149.

Zen 2, we see Threadripper go to 36 cores tops and 6 channel memory, with a changed layout (they move to 3 dies per chip for Threadripper) but retain the same socket. They start offering more budget boards (maybe we see some where it doesn't have the robust socket mount, has only 4 memory slots while higher end ones get 6). This is setting things up for what happens after that (with Zen 3). TR diverges from EPYC, in that the latter moves to a new socket (while Threadripper keeps the same, but it widens its market). So we'll see the space occupied by the original top Ryzen line (the $399 and up stuff) be on the Threadripper socket. Threadripper Zen 3 tops out at 48 cores and 8 channels (EPYC moves to 64 cores and 12 channels, still using the 4 die approach, but adding the extra memory channels, and also adds 4 socket support). For Threadripper and EPYC, Zen 3 is all DDR5.

I think we see EPYC 2 early next year. AMD is eager to capitalize while they can and I think 48 core EPYC with Zen 2 really sets the tone, they're going after Intel hard, in Intel's bread and butter. They surprise people and announce 12c/24t quad channel Zen 2 at CES (maybe companies show off prototypes but maybe running 8c/16t current chips, but promise there will be 12c/24t options, although maybe those don't really show up til Computex; and they steal Computex by showing off 8c/16t quad channel APUs and 36c/72t 6 channel Threadrippers).

I think we see in 2020 that they'll iterate (so Zen 2+) similar to this year (skip EPYC), but they had started on Zen 3 quickly (skipping Zen 2+ for EPYC, and aim to have it sampling, maybe even announced at the end of 2020 - just in EPYC mind you), it adds cores (64 per chip in EPYC, 16 per module), memory channels, I/O, and ups performance by pushing for higher clock speeds. The server chips become the initial platform for CPU architecture, and consumer lags, instead focusing on GPU improvements for its extra performance.

Early 2021 its EPYC 3, then Threadripper with 8 channels 48c/96t Zen 3 and stronger APUs with AM5 (and push DDR5 for graphics performance) at Computex. 2022 EPYC maybe adds 4 socket systems (but otherwise doesn't change), Threadripper with Zen 3+, and stronger APUs all DDR5.
 

moinmoin

Senior member
Jun 1, 2017
566
20
96
#7
AMD also still has to stick to the arrangement where Epyc and Ryzen is just a single die - due to lack of RD/staff resources and the additional costs of making a second chip. I'd say that is actually their policy and they won't abandon it that soon.
I agree, but not because I think AMD still lacks resources. Rather given the economical choice between designing different dies, and keeping a single die for the whole range of products but adapting that to different foundries, I fully expect AMD to go for the latter. GloFo also openly said AMD is free to make use of other foundries as well so I expect them to do just that, and not only for GPU parts.
 
Mar 11, 2004
17,409
56
126
#8
I agree, but not because I think AMD still lacks resources. Rather given the economical choice between designing different dies, and keeping a single die for the whole range of products but adapting that to different foundries, I fully expect AMD to go for the latter. GloFo also openly said AMD is free to make use of other foundries as well so I expect them to do just that, and not only for GPU parts.
And that's another potential benefit of the modular approach, they could theoretically mix GF and TSMC on a single chip. As long as they both meet the minimum spec, it should be fine. And if one is exceeding the other, they can bin chips that have more modules from that company and offer them for premium.

I like the general idea, but I have a question: Are we certain that AMD will continue the same "One die to rule them all" concept?

Speculation : What if they release a 3 CCX die AND a 2 CCX die, both on 7nm? With two foundries, we could even see the 3 CCX version at TSMC and a 2 CCX at GF at a latter
We already did see that, with the APUs. And I think we'll see them move the consumer line more in that direction. But I suppose it depends on if they add CCX or add cores to each CCX on how that would work out. There was a fair amount of speculation with regards to that, and there's even been some thinking that maybe they'd keep the core count the same but up the number of threads or something, but AMD has already straight up told people there is a 64c/128t chip being developed (I would guess it'll be Zen 3), so they are seemingly going keep the threads doubled per core for awhile.
 

NeoLuxembourg

Senior member
Oct 10, 2013
663
0
106
#9
We already did see that, with the APUs.
APUs are special as they require new dies anyway.

I was mostly talking about "normal" Ryzen, TR and Epyc. Having two CCX counts, aka two dies, could be interesting for yields/margins.

The funny part is that they could "play it safe" by using the same single die strategy and still beat Intel in most areas.
 

Jan Olšan

Senior member
Jan 12, 2017
255
4
76
#10
TSMC is the only one with any sort of production of 7nm. GloFo hasn't even reached risk or even completed the PDK. How do you think AMD already has samples in the lab?
EPYC 2 is 100% TSMC, nothing else makes sense.

They aren't willing to delay a thing, they paid a major charge to GloFo to be able to do this. EPYC 2 needs to come out as soon as possible to capitalize on Intel's 10nm delays. And since this will likely create a lot of unusable dies for EPYC, they'll most likely release it in consumer form too.

TSMC and GloFo 7nm are intentionally very similar to allow AMD to transfer their designs easily. I do expect the APU's to be made at GloFo, as their release timing makes sense to be manufactured there.
There is no way the processes are similar enough to be able to be optimally trargetted by the same design! And absolutely no way you could make chips on both using the same masks.
So basically if you wanted to make one generation of Ryzens on TSMC instead of GlobalFoundries, you risk big drop in WSA compliance. AMD has met the targets in 2017 mostly narrowly, and that was with the help of massive Polaris and Vega sellouts due to mining. What is actually likely now is that TSMC will get AMD's GPUs on 7nm, so you have to remove the GPU side from the equation. If you removed Ryzen CPUs and Epyc too, you would need APU sales to pick up all the slack and fill like billion $ in wafer orders (for 2018 and 2019, IIRC the WSA requirements AMD needs to meet are rising AFAIK). I think AMD's sales revenue would need to at least double or triple overall if they managed to raise APU sales that much :)
It would please me greatly but I don't think they can ramp APUs that high. Remember - it would have to be as much wafers as AMD ordered for all Ryzens, Epycs, Vegas and Polaris chips (plus legacy products), plus some 15-20 % more on top (I don't recall the exact numbers). The only way that could happen was if AMD converted all console APUs to GloFo, but as you can see the clients clearly want them on TSMC for more reliability. Sadly - this has cost AMD a lot of money.

If AMD doesn't meet WSA goals, it will pay several hundreds millions of $ to GloFo as compensation, *on top* of that they will be paying fines for the TSMC wafers as per the last WSA update, AND still on top of that they will have to pay the additional development ANDalso possibly pay extra (huge) costs for the Epyc masks if that die is being made in addition of GloFo Ryzen die.

In total, that's idunno, maybe 500 million $ that they could lose in this idea before they start making any money on it. It would probably kill most of their profit they could have in that year, do you think the TSMC advantages could ever compensate that? If you ask me, making a dualcore Ryzen die for desktops/laptops would be better use of the resources and would not come with those penalties.

(Well, if you disagree and think AMD can recoup the costs of masks+development and loss of ryzen-epyc synergy and also meet WSA requirement, I'd like to hear how of course. Naturally I can be wrong but these factors are not small, so overcoming them doesn't sound easy.)

PCI-E 5 is officially coming much sooner than PCI-E 4 was to PCI-E 3. Its been known for a long time. Google PCI-E 5.
PCIE4 took 6-7 years after PCIE3, for perspective. I'm not trying to claim pcie4 will take as much! But 3-4 years for 4->5 is still more reasonable IMHO. Side note: why should I google it? I have been watching hardware space for 6 years and writing about it for a living. I think I have a very good knowledge of all the info that is out there.
 
Last edited:

Abwx

Diamond Member
Apr 2, 2011
8,710
11
126
#11
GloFo hasn't even reached risk or even completed the PDK. How do you think AMD already has samples in the lab?
.
GF said recently that they delivered 7nm based CPU samples to AMD....
 

jpiniero

Diamond Member
Oct 1, 2010
5,805
42
126
#12
GF said recently that they delivered 7nm based CPU samples to AMD....
Probably just test samples though. After all, you could say the same thing about Intel's 10 nm for instance.

TSMC is in volume production now.

There is no way the processes are similar enough to be able to be optimally trargetted by the same design! And absolutely no way you could make chips on both using the same masks.
It sounds like GloFo changed things to help on this.
 

LightningZ71

Senior member
Mar 10, 2017
226
0
71
#13
It is certainly possible that AMD could go to a three die approach at 7nm:
an APU die with 2 X 4 core CCX or 1 X 6 core CCX and an iGPU that can be tailored from market to market. This will be a volume product at GloFo. [This will compete in the mobile/SFF space with Intel's mobile parts)
A pro-sumer die with 2 X 6 core CCX or 3 X 4 core CCX and no iGPU that is produced by GloFo in volume. It has applicability to SOME of the TR and EPYC stack. [This is the mainstream competition for desktop i5/i7/i9 and low end XEON]
A HEDT/Server die that is 4 X 4 core CCX that is produced by TSMC in limited quantities. It is expected that the first generation will have a high defect rate, so targeting is for at least one bad CCX per core. These are used for the 12 core dies for the 48 core EPYC products. The few that make it through with 16 functional cores are harvested for a 3800X chip. Later production with a refined process will produce 64 core EPYC products.

I don't see AMD targeting mainstream/high end desktop with an APU. It's wasted space for that market as much of it will have a dGPU anyway. I also believe that AMD is at or near the APU performance limit with the current APU architecture largely due to the limitations in DDR-4 bandwidth. There may be incremental gains at 7nm, especially if they throw in some sort of L4 cache on the die to help with memory contention. DDR 4 bandwidth will only increase marginally over the next two years and AMD is showing that their GPU tech can get heavily performance limited with limited memory bandwidth (aren't they all though?). So, a second generation APU with more cores, more L3 cache, and perhaps an L4 cache just makes sense as part of a performance growth strategy.
 

turtile

Senior member
Aug 19, 2014
414
0
91
#14
GF stated what they won't have enough capacity at 7nm to meet AMD's production needs. I'm going to assume that GF can't charge a fee if they can't meet AMD's needs...
 

CatMerc

Golden Member
Jul 16, 2016
1,105
6
106
#15
There is no way the processes are similar enough to be able to be optimally trargetted by the same design! And absolutely no way you could make chips on both using the same masks.
So basically if you wanted to make one generation of Ryzens on TSMC instead of GlobalFoundries, you risk big drop in WSA compliance. AMD has met the targets in 2017 mostly narrowly, and that was with the help of massive Polaris and Vega sellouts due to mining. What is actually likely now is that TSMC will get AMD's GPUs on 7nm, so you have to remove the GPU side from the equation. If you removed Ryzen CPUs and Epyc too, you would need APU sales to pick up all the slack and fill like billion $ in wafer orders (for 2018 and 2019, IIRC the WSA requirements AMD needs to meet are rising AFAIK). I think AMD's sales revenue would need to at least double or triple overall if they managed to raise APU sales that much :)
It would please me greatly but I don't think they can ramp APUs that high. Remember - it would have to be as much wafers as AMD ordered for all Ryzens, Epycs, Vegas and Polaris chips (plus legacy products), plus some 15-20 % more on top (I don't recall the exact numbers). The only way that could happen was if AMD converted all console APUs to GloFo, but as you can see the clients clearly want them on TSMC for more reliability. Sadly - this has cost AMD a lot of money.

If AMD doesn't meet WSA goals, it will pay several hundreds millions of $ to GloFo as compensation, *on top* of that they will be paying fines for the TSMC wafers as per the last WSA update, AND still on top of that they will have to pay the additional development ANDalso possibly pay extra (huge) costs for the Epyc masks if that die is being made in addition of GloFo Ryzen die.

In total, that's idunno, maybe 500 million $ that they could lose in this idea before they start making any money on it. It would probably kill most of their profit they could have in that year, do you think the TSMC advantages could ever compensate that? If you ask me, making a dualcore Ryzen die for desktops/laptops would be better use of the resources and would not come with those penalties.

(Well, if you disagree and think AMD can recoup the costs of masks+development and loss of ryzen-epyc synergy and also meet WSA requirement, I'd like to hear how of course. Naturally I can be wrong but these factors are not small, so overcoming them doesn't sound easy.)


PCIE4 took 6-7 years after PCIE3, for perspective. I'm not trying to claim pcie4 will take as much! But 3-4 years for 4->5 is still more reasonable IMHO. Side note: why should I google it? I have been watching hardware space for 6 years and writing about it for a living. I think I have a very good knowledge of all the info that is out there.
The terms of the WSA aren't public. I don't believe AMD "just barely" met the WSA. Considering the fantastic quarters they've had, they either took the dumbest terms ever, potentially killing the company if the ramp wasn't as quick as they expected, or they fulfilled it several times over.

As for process similarity, of course not the same masks. But they were designed to be similar enough to make it painless in layout and packaging. I do not believe for one second that it's too expensive for AMD to tape out two dies when their R&D budget is higher than it was for 6 years now.

And finally, quite frankly, Garry Patton in an interview with Anand said AMD will go with TSMC first for 7nm

PCI-E 5 is specifically made much faster than usual because of the explosion of its importance in the data center, and fear of being left behind by things like NVLINK. If you Googled as I asked you to, you would see that the PCI-E 5 spec is supposed to finalize in 2019, just two years after PCI-E 4's spec did.

GF said recently that they delivered 7nm based CPU samples to AMD....
Source?
 
Last edited:

CatMerc

Golden Member
Jul 16, 2016
1,105
6
106
#17
Infinity Fabric InterSocket controller can be easily upgraded to support Gen-Z. Which the 16-bidirectional SerDes can be used for two 2C connectors or more via bridges...

DGLTj-gUIAA6mvm.jpg:large
GenZ intends to replace DDR?
 

NostaSeronx

Platinum Member
Sep 18, 2011
2,188
9
106
#18
GenZ intends to replace DDR?
It intends to replace everything it can. SATA and SATA Express and M.2/U.2 is expected to be killed off with right-angled versions of 1C-4C.

SK Hynix has plans to do Gen-Z HBM3 DIMMs with the straights. (This is in the phase where it can be canned. So if it doesn't happen it isn't my fault.)
 
Last edited:

wahdangun

Senior member
Feb 3, 2011
992
1
106
#19
TSMC for Epyc 2 is not confirmed in any way. Forrest Norrod explicitly said that they are not revealing who makes it.

IMHO, there is still way too much riding on AMD's need to fulfil WSA order requerements and at the same time AMD also still has to stick to the arrangement where Epyc and Ryzen is just a single die - due to lack of RD/staff resources and the additional costs of making a second chip. I'd say that is actually their policy and they won't abandon it that soon.

Therefore, they virtually have to make Zen 2 CPU on GlobalFoundries. It is likely that they are willing to delay Zen 2 to wait for GloFo rather than jumping over to TSMC for the chip. Note that even if they used just TSMC for the Epyc/Ryzen CPU die, APU version would at least have to be on GloFo to cover at least part of WSA requirement. And that means you would still have doubled development efforts and costs on Zen 2. For these reasons, I'm not going to believe the TSMC conjectures until there is a solid proof.

I also doubt PCIe 5.0 will come that soon after 4.0. Gut feeling tells me that it won't appear on the first AM5 generation.

They still have Polaris successor to fullfil the WSA, and miner will make those WSA penalties disappear.
 

piesquared

Golden Member
Oct 16, 2006
1,583
1
136
#20
I think just by the timeline, roadmap and comments by respective company representatives that it's clear what is happening. TSMC is first with 7nm and AMD has demonstrated 7nm Radeon Instinct for release by the end of the year. GLOBALFOUNDRIES will be a fast follower on 7nm and AMD has Zen 2 running in their labs set to sample this year. I think it's fairly obvious which products are where. It makes sense for AMD to target lower volume high margin parts at the leading node at each foundry.
 
Last edited:

Jan Olšan

Senior member
Jan 12, 2017
255
4
76
#21
The terms of the WSA aren't public. I don't believe AMD "just barely" met the WSA. Considering the fantastic quarters they've had, they either took the dumbest terms ever, potentially killing the company if the ramp wasn't as quick as they expected, or they fulfilled it several times over.
The wafer target for 2017 was 1 billion IIRC. For the next years, I think somebody on reddit found them in some IR form, the numbers were like 1.2 and 1.3 billion (for a whole year).
And as for how much AMD spends on wafers, that is public, the information is in quarterly releases (CFO commentary details). IIRC, AMD landed almost exactly on the 1.0 billion mark. You have to remember that AMD's revenue didn't ramp up that much in 2017 and their unit sales didn't shoot up that much.

I do not believe for one second that it's too expensive for AMD to tape out two dies when their R&D budget is higher than it was for 6 years now.
Of course they can afford it. But they have to choose what chip they will spend the money on, they have to make return on that investment. Additional GPU chip for their very sparse graphics roadmap or additional lowend Ryzen APU would probably be wiser IMHO (I hope they are actually making that, tho), compared to split Epyc and Ryzen CPU into two different dies.

And finally, quite frankly, Garry Patton in an interview with Anand said AMD will go with TSMC first for 7nm
That probably just means Vega 20 (the 7nm Instinct).

If you Googled as I asked you to, you would see that the PCI-E 5 spec is supposed to finalize in 2019, just two years after PCI-E 4's spec did.
I know that very well, but it doesn't have to mean much. After all PCIe 4.0 will likely land 2019 at earliest and it was finalized last year. And that's with there being pressure on fast adoption and with the lengthy development probably making it easier to prepare for it. Because PCIe 4.0 will still be fresh, there will be less push to rush 5.0. More importantly, I think AMD might not want to change too many things for initial socket AM5 launch, that is why I said my hunch is it will come probably with second chip to hit that platform. They will plausibly want to test it for 5.0 but launch with 4.0 to mitigate risks. This though is just my guess, not something I was sure was going to happen exactly that way.
 

CatMerc

Golden Member
Jul 16, 2016
1,105
6
106
#22
The wafer target for 2017 was 1 billion IIRC. For the next years, I think somebody on reddit found them in some IR form, the numbers were like 1.2 and 1.3 billion (for a whole year).
And as for how much AMD spends on wafers, that is public, the information is in quarterly releases (CFO commentary details). IIRC, AMD landed almost exactly on the 1.0 billion mark. You have to remember that AMD's revenue didn't ramp up that much in 2017 and their unit sales didn't shoot up that much.


Of course they can afford it. But they have to choose what chip they will spend the money on, they have to make return on that investment. Additional GPU chip for their very sparse graphics roadmap or additional lowend Ryzen APU would probably be wiser IMHO (I hope they are actually making that, tho), compared to split Epyc and Ryzen CPU into two different dies.


That probably just means Vega 20 (the 7nm Instinct).


I know that very well, but it doesn't have to mean much. After all PCIe 4.0 will likely land 2019 at earliest and it was finalized last year. And that's with there being pressure on fast adoption and with the lengthy development probably making it easier to prepare for it. Because PCIe 4.0 will still be fresh, there will be less push to rush 5.0. More importantly, I think AMD might not want to change too many things for initial socket AM5 launch, that is why I said my hunch is it will come probably with second chip to hit that platform. They will plausibly want to test it for 5.0 but launch with 4.0 to mitigate risks. This though is just my guess, not something I was sure was going to happen exactly that way.
I guess we can just agree to disagree on the foundry thing. There's no point in taking this any further as there's not enough information to make a conclusive decision.

As for PCI-E 4, IBM's POWER 9 already supports it. PCI-E generations don't tend to take that long to implement, they're often just the same but with tighter signaling. I suspect Zen 2 will at the very least have the capability for it for special custom projects, if not the platform.
 

Vattila

Senior member
Oct 22, 2004
362
50
136
#23
Here is my intuition about the next couple of generations of Zen.

Firstly, about the fab use issue; as stated by Lisa Su, both TSMC and GlobalFoundries will be used. 7nm Vega is already confirmed to be made at TSMC. I suspect the primary plan is to produce "Zen 2" at GlobalFoundries. Why is AMD coy about it? Perhaps the simple reason is that AMD is still keeping options open.

While a process can look good on paper, a lot can go wrong from sampling to high-volume production. We have seen Intel's 10nm process turn out very badly. So, AMD may have a plan B for "Zen 2" at TSMC, and AMD may be cautious about stating the fab partner until high-volume production looks good.

I have set my expectations for the arrival of "Zen 2" to April 2019. I hope AMD will then do a concerted launch of Ryzen 3000 series and EPYC 2, with products rolling out throughout 2019 — including a progress update and ThreadRipper 3 announcement at Computex 2019 — thus following a nice yearly cadence.

Regarding "Zen 2" specifications and die configuration, the straightforward prediction is that the CCX will stay 4-core, and the die ("Starship") will have 3 CCXs for a total of 12 cores. This gives EPYC 2 a maximum of 48 cores in a multi-chip module with 4 dies, as expected, with ThreadRipper 3 sporting the same die and core counts. The mainstream Ryzen 3000 series will have 12, 9 and 6-core models in a single-die package.

However, the exciting and hard-to-predict part is what improvements we will see in the "Zen 2" core, un-core and Infinity Fabric interconnect. I expect these to be numerous. For example, it is not beyond the realm of possibility that EPYC 2 may scale up to 4 sockets, thus increasing compute density further ahead of Intel.

For their single-die APU, I suspect AMD will stay with 4 cores (single CCX) based on "Zen 2". Hopefully the integrated GPU will be upgraded to "Navi". The cost, power and size advantages from the 7nm shrink will be compelling, as will the architectural advance, so a small chip makes a lot of sense for the mainstream desktop and mobile segments.

To fight Intel's high-end mobile and small-form-factor offerings, I hope that AMD will finally realise a MCM chip comprising "Starship", "Navi" and low-cost high-bandwidth memory (HBM) interconnected by Infinity Fabric. With a maximum of 12 cores and better graphics, this chip will compete directly against Kaby Lake-G (Intel Core 8000G series with Radeon Vega graphics).

Regarding "Zen 3", I expect AMD will follow the same formula, but upping the number of CCXs to 4 for a maximum of 64 cores for EPYC 3 and Ryzen ThreadRipper 4000-series. If cost and density improvements allow, the single-die APU may get 2 CCXs at this point. Alternatively, they may stick with a single CCX to allow further market opportunity in the small-form-factor segments, such as tablets and embedded, while using the MCM approach to reach into the high end.
 
Last edited:

Thala

Senior member
Nov 12, 2014
598
1
106
#24
.I'd expect these processors to clock in the 4.5-4.6GHz boost range and have ~15% higher IPC.
15% higher IPC would be extremely surprising. Took intel several generation to get where they are now. 15% would essentially mean closing the gap to Intel.

Clockspeed estimate is based on ARM's claims of minor performance improvement with 7nm (on top of minor improvement of 10nm), along with a more complex Zen 2 design dropping clockspeeds a bit. Top mainstream will be 12 cores.
Not sure what quote from ARM you are referring to. I remember ARM said, that they only slightly increase the clock from 2.8GHz (10nm A75) to 3.0GHz (7nm A76) in order to stay in the same 750mW per core budget*. They did mention that you can run it at 3.3GHz too, while most likely not fitting into all-core-turbo + GPU 5W SoC budget. So from ARM this is always an power efficiency argument when they reason about clock-speeds and never a maximum achievable number.

*Thinking about this, a 16 core Cortex A76 SoC with below 15W TDP would be interesting, but thats off topic :)
 
Last edited:

KompuKare

Senior member
Jul 28, 2009
585
1
91
#25
15% higher IPC would be extremely surprising. Took intel several generation to get where they are now. 15% would essentially mean closing the gap to Intel
But the largest IPC increase Intel had since integrating the memory controller with Nehalem was between the first generation (Nehalem) and the second generation (Sandy Bridge).
As shown in, for instance, in this HardwareInfo article:
https://uk.hardware.info/reviews/62...l-ivy-bridge-sandy-bridge-and-nehalem-results
myYjbyX.png

Of course, there are no guarantees but precisely because Zen is a new design, I would expect version 2 to show a decent increase as they should have lots of low-hanging fruit.
 

ASK THE COMMUNITY