New Zen microarchitecture details

[AtenRa]

Implementing SOI on FinFet should lower the manufacturing cost, not increase it. Unless of course the labour / machine time is significantly cheaper than usual.

Manufacturing cost (less steps etc) is lower but because SOI substrate cost is considerably higher than Bulk, at the end FD-SOI on FinFets cost more than FF Bulk.

page 17 and 18

http://www.soiconsortium.org/pdf/Comparison%20study%20of%20FinFETs%20-%20SOI%20versus%20Bulk.pdf

Edit: This is another nice one

http://soitec.com/pdf/SoitecReport20110709.pdf

 

[Abwx]

Ah, okay. Thank you. I thought that the future designed cpu was going to be able to dynamically change the bias voltage depending on the workload. That way controlling power consumption of different sections of the cpu cores / soc. My mistake.

It can be dynamicaly done, as at wich speed that s another matter, although that should be fast enough to switch the CPU in a very low power mode, at 500MHz, when CPU usage does not require more than this frequency.

I see 22FDX only spanning the lowest 2 categories.

That s quite curious, although they talk of 2GHz in another paper, according to their datas CPUs works at 1.5GHz for 0.6V, if the transistor withstand 1V without losing its properties then frequencies up to 4GHz are possible.

 

[NostaSeronx]

Manufacturing cost (less steps etc) is lower but because SOI substrate cost is considerably higher than Bulk, at the end FD-SOI on FinFets cost more than FF Bulk.

22FDX HKMG Gate First is less complex than 28LPS PolySi Gate. [Samsung & GlobalFoundries; 28nm LPS : p-SiON for cost-sensitive applications that includes an easy migration path from older process nodes.]

 

[Phynaz]

GloFo's slides have been such a reliable source of truthful information in the past :^/

 

[el etro]

Manufacturing cost (less steps etc) is lower but because SOI substrate cost is considerably higher than Bulk, at the end FD-SOI on FinFets cost more than FF Bulk.

page 17 and 18

http://www.soiconsortium.org/pdf/Comparison%20study%20of%20FinFETs%20-%20SOI%20versus%20Bulk.pdf

Edit: This is another nice one

http://soitec.com/pdf/SoitecReport20110709.pdf

First one is what i am talking about. Just would like to know the SOIff performance on 4GHz chips, maybe being SOI will make the chip leak less energy at 4GHz+.
All of my interest comes because IBM 14SOIff is just around the corner, maybe it will be ready for pureplay fab at GF. Also IBM Power9 will be fabbed on it, its capacity attracts our attention.

 

[NostaSeronx]

GlobalFoundries 14nm High Performance GF14HP;
14nm SOI FinFETs

14nm SOI FinFETs vs Trigate/DG Bulk FinFETs (addition to: http://forums.anandtech.com/showpost.php?p=38221736&postcount=1151)
~6% / ~10% performance boost,
2x / 5x leakage reduction,
Short channel effects increase,
Variability is decreased in which straining and doping can be used with minimal cost.

IBM is also dealing with this so the above might not be completely accurate;
https://www.google.com/patents/US9093558

Integration of multiple threshold voltage devices for complementary metal oxide semiconductor using full metal gate;

• Enables both Vt modulation as well as self-aligned contacts
• Vt shift through materials and process
• Reduces the need or eliminates channel doping (avoids short-channel penalty)
• Reduces the need or eliminates ground plane/back gate (avoids severe integration challenges)
• Enables simple process flow with gate-first integration
• Extends to planar PDSOI (partially depleted SOI)/bulk and FinFETs

Model 1;
http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5984620
Model 2;
http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=7369940

More patents;
https://www.google.com/patents/US20140162447
https://www.google.com/patents/US8623730
https://www.google.com/patents/US8415677 (Model 1)

Every indication though shows 14nm SOI FinFETs being Double Gate(Trigate with a Ground) with Replacement Metal Gate.

 

[The Stilt]

Anyone knows who was the project leader / chief architect for AMD Bobcat cores (14h)?

Certain aspects in Zen reminds me of Bobcat (not the cores itself). I've never seen such configuration anywhere else before besides the Bobcat and if I didn't know better I'd probably say I'm looking at an ARM ASIC

I didn't particularly like how the things were done in Bobcat, but at least in Zen this aspect is significantly more precise than it was before. It will give some additional pain for tinkerers like me and to people who need to add software support to detect certain parameters of the CPU.

The "power management" on Zen can be up to 8x more precise than on any previous AMD designs, which makes me think (even more) that the operating frequency of Zen will be rather strict to either direction. I cannot believe that the power budget would be so constrained to justify the implementation of a highly precise and complex control such as this.

I have no idea what the clocks on Zen will be, however I can tell for sure that the 3.0GHz displayed in (AIDA in BnC April Fools) wasn't real. Or maybe it was, but at least not in the way it was presented to us. Nothing else in the displayed information added up either.

 

[el etro]

Thanks Seronx!

We are at one year from Power9, 14GHP is probably at three quarters from mass production from now. Will be great if IBM process brings Intel 14FF density(or close) and is better suited for HP applications!

 

[Arachnotronic]

Anyone knows who was the project leader / chief architect for AMD Bobcat cores (14h)?

Brad Burgess, now working at Samsung.

 

[NostaSeronx]

Anyone knows who was the project leader / chief architect for AMD Bobcat cores (14h)?

Brad Burgess(King of Bobcat), he went Samsung with;
Jim Mergard(King of Brazos) <-- went Apple.
Frank Helms(Fusion Architect)
Patrick Patla(Server Architect)

The "power management" on Zen can be up to 8x more precise than on any previous AMD designs, which makes me think (even more) that the operating frequency of Zen will be rather strict to either direction. I cannot believe that the power budget would be so constrained to justify the implementation of a highly precise and complex control such as this.

Zen most likely fuses two power management types;
Kaveri/Carrizo provides -> AVFS, APM, AFS
Puma/Puma+ provides -> STAPM, Accurate-Thermal Sensors inside AVFS units.

Will be great if IBM process brings Intel 14FF density(or close) and is better suited for HP applications!

My analysis from estimated (Intel from HP-6T 22nm) and (IBM HP-16T TCAM and HP-8T SRAM 14nm SOI)
GlobalFoundries 14HP; High Performance 6T SRAM Bit-cell; ~0.0801 &#956;m²
Samsung 14nm LPP; High Performance 6T SRAM Bit-cell; 0.08 &#956;m²
Intel 14nm; High Performance 6T SRAM Bit-cell; ~0.71 &#956;m²

If IBM went aggressive and adopted Tri-gate FMG, w/ 10nm MOL. Then, the SRAM could possibly shrink to ~0.065 &#956;m².

 

[Lepton87]

Thanks Seronx!

We are at one year from Power9, 14GHP is probably at three quarters from mass production from now. Will be great if IBM process brings Intel 14FF density(or close) and is better suited for HP applications!

Are you interested in Power9? It should top Intel's CPUs in performance, especially in single thread and probably in multi as well at least initially just like Power8 did, but man was it and still is expensive. AMD will not use anything other than bulk nodes.

 

[NostaSeronx]

AMD will not use anything other than bulk nodes.

AMD will use any node they wish. It could be bulk, PDSOI, FDSOI, FinFET, SOI FinFET, SOI Nanowire, or Vertical, etc.

The requirements for adoption of said nodes are;
- Multi-foundry (Not necessarily Samsung+GlobalFoundries, but Fab 1 + Fab 8, or Fab 8 + S2(Samsung), or Fab 8 + Fab 12(TSMC) + Fab 14(TSMC), etc.)
- Multi-tool & ip (Cadence, Mentor Graphics, Synopsys, Verisilicon, etc.)
- Multi-contract (einfochips, Soctronics, Synpase Design, etc.)
- Popular demand thus overall lower cost.

 

[Dresdenboy]

Anyone knows who was the project leader / chief architect for AMD Bobcat cores (14h)?

Certain aspects in Zen reminds me of Bobcat (not the cores itself). I've never seen such configuration anywhere else before besides the Bobcat and if I didn't know better I'd probably say I'm looking at an ARM ASIC

I didn't particularly like how the things were done in Bobcat, but at least in Zen this aspect is significantly more precise than it was before. It will give some additional pain for tinkerers like me and to people who need to add software support to detect certain parameters of the CPU.

The "power management" on Zen can be up to 8x more precise than on any previous AMD designs, which makes me think (even more) that the operating frequency of Zen will be rather strict to either direction. I cannot believe that the power budget would be so constrained to justify the implementation of a highly precise and complex control such as this.

I have no idea what the clocks on Zen will be, however I can tell for sure that the 3.0GHz displayed in (AIDA in BnC April Fools) wasn't real. Or maybe it was, but at least not in the way it was presented to us. Nothing else in the displayed information added up either.

A more precise power mgmt could simply avoid wasting too much performance for big margins, transition losses, etc. The better, if they did that before.

Zen team has a lot of Cat core "veterans". ARM ASIC does sound right due to Zen/K12 overlap.

 

[The Stilt]

A more precise power mgmt could simply avoid wasting too much performance for big margins, transition losses, etc. The better, if they did that before.

Being this precise would be a complete overkill, since even the old implementation allowed more than sufficient control, at least for the frequency range achieved on the older process / design.

Frequency control this accurate has to do something with the process itself, because I don't think this much of additional effort can be simply justified by the extremely minor additional efficiency.

 

[majord]

I can see where the Stilt is coming from. Tight tolerances almost always indicate a situation where you're essentially 'fine tuning ' to extract the last Mhz.

However, I don't think it's necessarily an indication of limited frequency headroom - but something more along the lines of a smaller stability margin than we're used to, and / or a process which is more sensitive to voltage than temperature, - thus requiring more granular Voltage control in order to speed bin appropriately (which I think Dresden was alluding to)

It's interesting to see how Nvidia has gone to similar lengths with Pascal, with extremely tight regulation.

 

[AtenRa]

http://www.amdcomputex.com.tw/

 

[LTC8K6]

Is the 7th gen going to be numbered 8XXX? We obviously already have 7K series APUs.

 

[The Stilt]

"7th Gen" = 9K series.

The only new thing in this "7th" series is Stoney Ridge, while Bristol Ridge is technically identical to Carrizo. Carrizo with single channel memory, a single CPU CU and three GPU CUs aka Stoney Ridge doesn't make me too exited D:

 

[The Stilt]

It seems that the final and the correct term is "up to" :sneaky:
Interesting, since I think we have heard not only an exact figure but also "over" term being used during the past year...

Makes kind of sense, thou.

 

[Dresdenboy]

It seems that the final and the correct term is "up to" :sneaky:
Interesting, since I think we have heard not only an exact figure but also "over" term being used during the past year...

Makes kind of sense, thou.

If you're talking x265, I'm not surprised.

Even having lots of latency, throughput numbers, sizes for instns, caches, mem leaves some prediction accuracy at the table. What's the performance impact of being able to handle 5 or 10 concurrent L2 cache accesses?

 

[The Stilt]

If you're talking x265, I'm not surprised.

Even having lots of latency, throughput numbers, sizes for instns, caches, mem leaves some prediction accuracy at the table. What's the performance impact of being able to handle 5 or 10 concurrent L2 cache accesses?

No I'm not talking about the actual performance, since I have no idea what it is like. I'm am talking about the terms, which will be ultimately used for marketing.

Previously we have heard an exact figure or even "excess" a certain figure. Now there seems to be "up to" prefix to this certain figure.

 

[NostaSeronx]

The only new thing in this "7th" series is Stoney Ridge, while Bristol Ridge is technically identical to Carrizo. Carrizo with single channel memory, a single CPU CU and three GPU CUs aka Stoney Ridge doesn't make me too exited D:

Apparently, Stoney Ridge has an FIPMIC(Fully Integrated Power Management Integrated Circuit), not just FIVR(Fully Integrated Voltage Regulation).

For those that are like what is a PMIC compared to a FIVR?

PMIC;

FIVR;

VCC only -> FIVR
Everything possible -> PMIC

Improved suspend/resume time by 70%
Reduced driver S3/S4 resume latency by 70%

 

[The Stilt]

Apparently, Stoney Ridge has an FIPMIC(Fully Integrated Power Management Integrated Circuit), not just FIVR(Fully Integrated Voltage Regulation).

No.

 

[Silverforce11]

&#8220;Zen will compete with Intel on performance, power and specifications &#8211; not just price,&#8221; -John Taylor Corporate VP, worldwide marketing.

http://www.itwire.com/it-industry-n...ll-favourably-compete-with-intel-skylake.html

Bold words, claims competitive vs Skylake.

Not only on price, but everything else. Some serious trolling or they are confident.

 

[frozentundra123456]

“Zen will compete with Intel on performance, power and specifications – not just price,” -John Taylor Corporate VP, worldwide marketing.

http://www.itwire.com/it-industry-n...ll-favourably-compete-with-intel-skylake.html

Bold words, claims competitive vs Skylake.

Not only on price, but everything else. Some serious trolling or they are confident.

They are competing with Intel and nVidia now. They are just losing.

Seriously though, he is a marketing guy, what is he supposed to say? Dont bother waiting for our stuff, we arent really going to be competitive? It seems highly likely Zen will be much more competitive than what they have now, but "competitive" could mean a variety of things.