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Discussion in 'CPUs and Overclocking' started by Dresdenboy, Mar 1, 2016.
It looks to me on the last ppt that zen is like 2.8x excavator?
Yeaa wtf?. Noticed it as well. To me the ppt just look like a mess with some random techincal nonsense tacked on. They could either give more precise performance information or more consistent arch description or more apecific like eg latency numbers for cache. Imo its just not good enough. Who is the audience for this meaningless crap?
Well the slide states 40%, dunno where you see 2.8x?
I think he's calling out how BS the 'graph' looks. Of course, it's just a glossy marketing creation and not an actual graph.
I see multiple signs of problems med gf 14nm
Fmax as evidenced by polaris zen roumers and A10 on ss vs tsmc
Process variation as seen by underclocking polaris results
Yield issues as said by Lisa S
But more worrisome is imo looking at polaris cards high idle power usage eg seen at thg tests. Is that a sign of high leakage?
Generally, high leakage = higher clockspeed potential, which is something allegedly not offered by 14nm LPP. But we'll have to wait and see how it really works out in retail silicon.
I really wonder if that's true anymore with FinFET, due to transistor heating issues and performance related to that. I've heard that transistor heating is a bigger issue with FinFET, and if there's more power flowing through a junction, due to high leakage, won't that mean more heat too?
Dunno, FinFETs may change all the rules with respect to the expected behavior of high-leakage parts. Though we can probably look at the behavior of individual samples of Polaris 10 and compare ASIC quality numbers vs. clockspeed behaviors to guess at how 14nm LPP's clockspeed potential varies with leakage current.
Kudos to Dresdenboy.
Yep. Time for him to renew his avatar
Lisa seems very confident saying: "The take away is we -absolutely- reached our performance targets"
And i notice its "performance" lol
There is no yield issues. Lisa said no such thing. Also Polaris "high power" usage only manifests itself when more than one monitor is used, and it can be directly traced to the memory clock. The memory goes into high p-state with multiple monitors. 8gb of rx480 VRAM uses 40 watts at max clock. So it's more like a software/vbios optimization issue, but it certainly has nothing to do with the Polaris 14nm process.
I hope they are competitive so that CPU prices come down across the board. But I doubt Intel's plan for 2017 is to underclock their last year's CPU.
Haha, they admitted to underclocking the Intel CPU.
Another AMD Marketing win.
It's a clock for clock comparison, Intel does the same thing when showcasing new architectures compared to their previous ones.
Wow, quite the detective you are. It's obviously meant as a clock to clock comparison, your trolling is getting tiresome.
Their problem for years has been IPC. This was a demo demonstrating IPC equivalent to Broadwell.
I can see it now,
"AMD undercuts Intel 8Core 16Threads CPU Price by 40% to $999"
Bye bye 6-Core 12T mainstream
As an amd fan who has been forced to buy intel for quite a number of years now, I'm pretty excited about this new arch. I have to think about what I'm going to do when this comes out. I'll be coming from ivy bridge when it's time to upgrade, so it's going to be a whole platform change whether I go intel or amd, so this is really meaningful to me. Looks like it might end up being a virtual tie in terms of performance at a given price point. If that's the case I'll be going back to amd this round.
Yes, I know. But find a better way, don't go on stage saying "For this comparison we handicapped our competitors chip". I mean come on, that's the same as saying "Our competitors product is better than ours".
The point is to highlight your products advantages, not your competitors.
Now that i think about the presentation, i dont know if ZEN has the same IPC as Broadwell-E or if ZENs SMT implementation has higher scaling than Intels.
This Demo was about throughput at the same clocks and not single Thread perrformance, since both CPUs used SMT and not just single Thread per core
edit: The good part is (for Servers) that Throughput is competitive at the same clocks, we have to wait and see if it is competitive at the same power as well.
Well there are a couple of assumptions I made on this point. First of all we're apparently looking at early silicon which may not be capable of running with absolute stability at the clockspeeds amd will be ultimately targeting. That's a reasonable assumption I think. The second is that they wanted to make this demonstration with the highest end intel chip they could, which would come with all the bells and whistles required to maximize ipc at any clockspeed. They could have chosen a lower end chip that normally runs at 3ghz, but then people would be complaining about amd being afraid to match their chip up against intel's best. No I think what they did was appropriate for what they were trying to demonstrate.
Good news, sounds like they fixed the caches.
That's nice post. I didn't think it like that.
With time GF will improve their 14nm node and we'll get some good consumer chips. The frequency is already good for servers, IPC looks good too. Hopefully cpus will become more competitive from next year.