Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Covfefe]

Totally different weight class

Okay, but you implied that the e-cores aren't competitive with ARM cores in PPA. I don't see any evidence for that.

If power consumption is the issue, we can account for that. David Huang's 255h review has a perf/watt graph. Skymont at 4W is still 15% faster than the A725 in GB10. 15% more performance for 30% more area at similar wattage is very competitive.

 

[Geddagod]

47% higher peak performance as well ... ability to scale to multiple design be it laptop or desktop?

Why not just compare it to the X4, which is ~10% bigger without the L2 sram cells, meaning without the other extra L2 logic it should be similar in size if not outright smaller?
Also, a 4c X4 cluster is smaller than a 4c Skymont cluster, only counting up to the L2.

An iso area comparison makes much more sense.

Okay, but you implied that the e-cores aren't competitive with ARM cores in PPA. I don't see any evidence for that.

Look at the X4 in the mediatek 9400 and you would see a very different picture. Similar peak perf, but both smaller and much better power.

If power consumption is the issue, we can account for that. David Huang's 255h review has a perf/watt graph. Skymont at 4W is still 15% faster than the A725 in GB10. 15% more performance for 30% more area at similar wattage is very competitive.

How exactly do you know how many watts a A725 uses in GB10?
The A725 in the Xring clocks 21% higher than the one in the GB10 and consumes ~2 watts from Geekerwan's specint testing. The GB10 A725 power consumption has to be tiny.

We can actually use that graph and relativize it to Geekerwan's SOC power (for mobile phone) power graphs to get some interesting results. Mind you, the projected Geekerwan numbers should be the worst case scenario for ARM here, since Intel is projecting just core+cache (actually for the E-cores the L2 cache isn't in the figure) while for Geekerwan the entire SOC is being measured, including the power hungry mem PHYs. As much as you can subtract them from idle, when they are fired up they still consume extra power....

I did this as a fun thought experiment a lil while ago for the 5/4nm class cores, but using that graph you gave:

As a reminder, this is the absolute worse case graph for ARM, due to the way geekerwan is testing the power.

 

[Covfefe]

Look at the X4 in the mediatek 9400 and you would see a very different picture. Similar peak perf, but both smaller and much better power.

Huh? From what I've seen, X4 is bigger than Skymont, not smaller.

How exactly do you know how many watts a A725 uses in GB10?
The A725 in the Xring clocks 21% higher than the one in the GB10 and consumes ~2 watts from Geekerwan's specint testing. The GB10 A725 power consumption has to be tiny.

We can actually use that graph and relativize it to Geekerwan's SOC power (for mobile phone) power graphs to get some interesting results. Mind you, the projected Geekerwan numbers should be the worst case scenario for ARM here, since Intel is projecting just core+cache (actually for the E-cores the L2 cache isn't in the figure) while for Geekerwan the entire SOC is being measured, including the power hungry mem PHYs. As much as you can subtract them from idle, when they are fired up they still consume extra power....

I did this as a fun thought experiment a lil while ago for the 5/4nm class cores, but using that graph you gave:

As a reminder, this is the absolute worse case graph for ARM, due to the way geekerwan is testing the power.

1. You can't compare SPEC results done under different test conditions.
2. Geekerwan's power consumption measurements for phone SOCs are highly questionable. If we were to compare the 8 Elite to the X Elite. The phone SOC appears to be over 3x more efficient at every point on the curve.

Either his numbers are wrong, or phones are somehow far more efficient than laptops. Either way his phone power consumption numbers are useless when comparing to laptop CPUs.

 

[Geddagod]

Huh? From what I've seen, X4 is bigger than Skymont, not smaller.

The X4 has a private L2 cache. Skymont does not.
You can compare it either as a 4x X4 cluster vs the Skymont 4c cluster, or a X4 core without L2 SRAM arrays vs a Skymont core, and you get it being smaller or similar in area.

You can't compare SPEC results done under different test conditions.

I didn't. At least not directly. I used relative scaling based on Huang's results vs Geekerwan's results based on the Oryon V2-L core.

Geekerwan's power consumption measurements for phone SOCs are highly questionable. If we were to compare the 8 Elite to the X Elite. The phone SOC appears to be over 3x more efficient at every point on the curve.

It's understandable once one considers how much lower the uncore power for a smartphone chipset has to be vs laptop chips.

Here's an example-
Say a smartphone has a uncore power of 1 watt, and a core scores 5 points at 1 watts of power. Now say a laptop chip has an uncore power of 3 watts, and uses the same core.
So the smartphone, from a SOC power perspective, takes 2 watts to score 5 points, however the laptop chip, due to the way higher uncore power, takes 4 watts to do so, esentially 2x the perf/watt.

That and the 8 elite is a node shrink vs X elite.

Either way his phone power consumption numbers are useless when comparing to laptop CPUs.

Well that's why I didn't use SOC power. I used the core power graph you provided, vs the SOC power for the mobile phones from Geekerwan. Meaning that the ARM cores are disadvantaged, while the x86 cores on the graph you provided are at a large advantage. This is especially true at lower power, where the uncore power takes up a larger percentage of total SOC power in comparison to core power.

 

[Covfefe]

The X4 has a private L2 cache. Skymont does not.
You can compare it either as a 4x X4 cluster vs the Skymont 4c cluster, or a X4 core without L2 SRAM arrays vs a Skymont core, and you get it being smaller or similar in area.

Whether you measure both with L2 or both without L2, Skymont is smaller.

The X4 has a private L2 cache. Skymont does not.
You can compare it either as a 4x X4 cluster vs the Skymont 4c cluster, or a X4 core without L2 SRAM arrays vs a Skymont core, and you get it being smaller or similar in area.

I didn't. At least not directly. I used relative scaling based on Huang's results vs Geekerwan's results based on the Oryon V2-L core.

It's understandable once one considers how much lower the uncore power for a smartphone chipset has to be vs laptop chips.

Here's an example-
Say a smartphone has a uncore power of 1 watt, and a core scores 5 points at 1 watts of power. Now say a laptop chip has an uncore power of 3 watts, and uses the same core.
So the smartphone, from a SOC power perspective, takes 2 watts to score 5 points, however the laptop chip, due to the way higher uncore power, takes 4 watts to do so, esentially 2x the perf/watt.

That and the 8 elite is a node shrink vs X elite.

Well that's why I didn't use SOC power. I used the core power graph you provided, vs the SOC power for the mobile phones from Geekerwan. Meaning that the ARM cores are disadvantaged, while the x86 cores on the graph you provided are at a large advantage. This is especially true at lower power, where the uncore power takes up a larger percentage of total SOC power in comparison to core power.

I know it's measured differently. But the discrepancy is so huge that the higher consumption of the laptop chassis can't account for it. Even if you're generous to the mobile chip and move the X Elite curve 4 watts to the left, the conclusion is the same. The 8 Elite is supposedly 2x more efficient past the 6.25 watt line. One node shrink and minor core improvements can't account for that.

 

[511]

The X4 has a private L2 cache. Skymont does not.
You can compare it either as a 4x X4 cluster vs the Skymont 4c cluster, or a X4 core without L2 SRAM arrays vs a Skymont core, and you get it being smaller or similar in area.

How much L2 Does X4 has ?

 

[Geddagod]

Whether you measure both with L2 or both without L2, Skymont is smaller.

You can measure it yourself. Kurnal on twitter for die shots of the 9400.

Without the L2 sram arrays, it's ~8% larger, however once one accounts for the extra L2 control logic and tags, it should at least be similar in area.
If you measure it by comparing 4x clusters, it's outright smaller.

What's interesting about the X4 in the 9400 is that it appears to fill the same niche as Skymont fills- pure perf/mm2 cores. Both target high peak perf and sacrifice a bunch of area (and seemingly power through a lot of the V/F curve) to do so.

I know it's measured differently. But the discrepancy is so huge that the higher consumption of the laptop chassis can't account for it.

It definitely can. Esp once you also consider Geekerwan's testing methodology- not software, but like Qcomm, it's idle normalized hardware readings. He applied this to laptops too, because Qcomm doesn't give power readings via the device itself or through software.

Besides, I'm not using Geekerwan's laptop testing at all, just his mobile numbers. Your main point of contention appears to be the how the mobile numbers are so low. Well, I assure you, you can find data from other reviewers as well confirming that yes, the SOC power actually can scale that low:

Moreover you can also see how the results are very similar to what Geekerwan has. The Xring O1 and Oryon V2 cores have very similar perf and perf/watt curves, like Geekerwan's data showed. Moreover, you can see a very similar ~3.7x ratio between the peak perf and the Vmin of Oryon V2.
Ofc the absolute numbers are different, but the important thing is that relatively everything between the two graphs are similar.

How much L2 Does X4 has ?

1MB per core.

 

[511]

1MB per core.

than it's unlikely cause on A725 1MB L2 is like 0.3mm2 in 14 Blocks of 72KiB

 

[Geddagod]

than it's unlikely cause on A725 1MB L2 is like 0.3mm2 in 14 Blocks of 72KiB

The 9400 die shot is online (kurnal, twitter). It's very easy to use paint to pixel count.
I don't mind being fact checked... but like one can go through the effort to actually fact check me lol.

 

[DavidC1]

You can remove the entire FPU block on Zen 5C, and the L2, and you would still get a core larger than Skymont. I'm extremely doubtful that it performs as well as Skymont either. Prob will have decentish power though, unlike Skymont.

Skymont is big part of why Lunarlake achieves decent light-medium load battery life. So it can scale pretty well.

Things are so bad that one can compare the geekerwan smartphone core+cache power (should be a large overestimate) vs the AMD/Intel modeled core+cache power and still have ARM either leading or at worst, on par, in perf/watt.
Even iso node (X4).

Bad Intel/AMD uncore is part of the reason. The CPU is like a driver in a horse carriage wagon with multiple leashes. When the non-CPU part cannot power down, the amount of power the CPU itself can power down is also limited. It's because they are not motivated to make low power since they are complacent in the x86 reality distortion field, just like it's fans are.

 

[poke01]

Bad Intel/AMD uncore is part of the reason. The CPU is like a driver in a horse carriage wagon with multiple leashes. When the non-CPU part cannot power down, the amount of power the CPU itself can power down is also limited. It's because they are not motivated to make low power since they are complacent in the x86 reality distortion field, just like it's fans are.

Lunar Lake solved it. Its uncore and fabrics is excellent
What the problem with lunar lake is Lion Cove. The rest of the SoC is A+

 

[Thunder 57]

Skymont is big part of why Lunarlake achieves decent light-medium load battery life. So it can scale pretty well.

Bad Intel/AMD uncore is part of the reason. The CPU is like a driver in a horse carriage wagon with multiple leashes. When the non-CPU part cannot power down, the amount of power the CPU itself can power down is also limited. It's because they are not motivated to make low power since they are complacent in the x86 reality distortion field, just like it's fans are.

Is there really a new category of "fans" of ARM vs x86? They are serving different markets ATM. They have went with different design choices.

 

[511]

So PTL First SKU is shipping to Customers

https://seekingalpha.com/article/4850032-intel-corporation-intc-presents-at-ubs-global-technology-and-ai-conference-2025-transcript

 

[techjunkie123]

5 units sitting somewhere?

 

[511]

View attachment 134813
5 units sitting somewhere?

Nice meme but it shipping out of Oregon in quantity if it was a single SKU and a single Unit pat delivered to Lenovo on stage last year.

 

[dullard]

Nice meme but it shipping out of Oregon in quantity if it was a single SKU and a single Unit pat delivered to Lenovo on stage last year.

We've already had leaks from benchmarks of 338H, 358H, and 386H Panther Lake chips. So, at a minimum 3 chips have been sold.

Honestly, it seems like people are stretching so hard to say that Intel did or did not sell Panther Lake this year. The reality will disappoint both sides: Intel did sell Panther Lake chips in 2025, but not many.

 

[dullard]

Intel did not order enough TSMC tiles for Lunar Lake and Arrow Lake. And Intel could not get enough wafers for Granite Rapids. Basically Intel is selling everything it has. With the industry-wide shortage of rare earths, substrates, and wafers (caused by AI, data centers, and politics) I expect this to go on for at least another year. Intel shot itself in the foot though by underordering earlier.

Intel admits it needs more Core Ultra 200-series wafers — 'If we had more Lunar Lake wafers, we would be selling more Lunar Lake'

Cannot get enough wafers from TSMC.

www.tomshardware.com

 

[jpiniero]

Intel did not order enough TSMC tiles for Lunar Lake and Arrow Lake.

Didn't Intel recently just hike prices on Raptor Lake because not enough Arrow was being bought? Maybe cut Raptor back down?

 

[Magio]

Honestly, it seems like people are stretching so hard to say that Intel did or did not sell Panther Lake this year. The reality will disappoint both sides: Intel did sell Panther Lake chips in 2025, but not many.

Let's see what CES has in store and when those design wins ship in quantity. It's clear that PTL missed Intel's usual EEP window, but if the CES launch is at a satisfactory scale and the ramp through 2026 follows suit then that's not too big a deal.

 

[511]

Intel did not order enough TSMC tiles for Lunar Lake and Arrow Lake. And Intel could not get enough wafers for Granite Rapids. Basically Intel is selling everything it has. With the industry-wide shortage of rare earths, substrates, and wafers (caused by AI, data centers, and politics) I expect this to go on for at least another year. Intel shot itself in the foot though by underordering earlier.

Intel admits it needs more Core Ultra 200-series wafers — 'If we had more Lunar Lake wafers, we would be selling more Lunar Lake'

Cannot get enough wafers from TSMC.

www.tomshardware.com

They expect Q1 26 to be the worst supply time guess PTL ramp is the only way to save them

 

[LightningZ71]

Sad part is that they had the chance to make a halo part on Intel 7 with Bartlett Lake. Re-enabled AVX512, ECC, and resolve the crashing issue with the platform and they could have sold it for a premium as both a Xeon and a K series.

 

[dullard]

Didn't Intel recently just hike prices on Raptor Lake because not enough Arrow was being bought?

First half of that sentence is true. The second half is just wishful thinking from certain people. The reality is Arrow Lake is selling out.

Raw materials and fab space are in drastic short supply. CPUs, hard drives, GPUs, memory, etc. are all increasing in price out due to intense demand for the raw materials. End of story. High demand leads to increases in prices.

 

[Magio]

They expect Q1 26 to be the worst supply time guess PTL ramp is the only way to save them

The funny thing is OEMs will have depleted their RAM stockpiles by the time PTL has fully ramped so pricing is going to be a bitch.

 

[dullard]

The funny thing is OEMs will have depleted their RAM stockpiles by the time PTL has fully ramped so pricing is going to be a bitch.

That could very well be true. It might be hard to find RAM in the spring time.

That said, manufacturers tend to focus on producing high-profit items in times of shortages. In the case of RAM, that would be their top speed memory: like DDR5-6800 and DDR5-7200 that Panther Lake will use. Expect the slow speed RAM and small capacity RAM sticks to be especially hard to find.

The RAM shortage is expected through Q4 2027. So, it doesn't affect just Panther Lake.

 

[Joe NYC]

Intel did not order enough TSMC tiles for Lunar Lake and Arrow Lake. And Intel could not get enough wafers for Granite Rapids. Basically Intel is selling everything it has. With the industry-wide shortage of rare earths, substrates, and wafers (caused by AI, data centers, and politics) I expect this to go on for at least another year. Intel shot itself in the foot though by underordering earlier.

Intel admits it needs more Core Ultra 200-series wafers — 'If we had more Lunar Lake wafers, we would be selling more Lunar Lake'

Cannot get enough wafers from TSMC.

www.tomshardware.com

I have not gone through the full transcript, but I came across a quote from that conference where the Intel presenter said the shortages would persist through Q1, Q1 being the worst.

BTW, Lisa was at the same conference, and she did not mention any shortages on her end. So what is unclear is if these are (for now) mostly Intel specific or industry wide.

Further out, 1-3 years, TSMC CEO did say that people are coming to him requesting more wafers that he can deliver.