Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[511]

https://twitter.com/x/status/1998369126952100101

 

[mikk]

This looks like 10% better IPC from the Cove which is surprisingly good for a shrink generation. Maybe the improved fabric also helps.

 

[dullard]

This looks like 10% better IPC from the Cove which is surprisingly good for a shrink generation. Maybe the improved fabric also helps.

Geekbench values are strongly impacted by memory speed. The faster DDR5 could account for a lot of the improvement. Unfortunately, neither memory speed nor power consumption are not listed in the link.

 

[jdubs03]

Geekbench values are strongly impacted by memory speed. The faster DDR5 could account for a lot of the improvement. Unfortunately, neither memory speed nor power consumption are not listed in the link.

Indeed, but it might be the case that the comparison is apples to apples.

This would be on the high side favoring ARL:

ASUSTeK COMPUTER INC. ASUS Zenbook Duo UX8406CA_UX8406CA - Geekbench

Benchmark results for an ASUSTeK COMPUTER INC. ASUS Zenbook Duo UX8406CA_UX8406CA with an Intel Core Ultra 9 285H processor.

browser.geekbench.com

 

[511]

Indeed, but it might be the case that the comparison is apples to apples.

This would be on the high side favoring ARL:

ASUSTeK COMPUTER INC. ASUS Zenbook Duo UX8406CA_UX8406CA - Geekbench

Benchmark results for an ASUSTeK COMPUTER INC. ASUS Zenbook Duo UX8406CA_UX8406CA with an Intel Core Ultra 9 285H processor.

browser.geekbench.com

Default string Default string vs ASUSTeK COMPUTER INC. ASUS Zenbook Duo UX8406CA_UX8406CA - Geekbench

browser.geekbench.com

so roughly 5-6% higher perf/clock for PTL

 

[jdubs03]

Default string Default string vs ASUSTeK COMPUTER INC. ASUS Zenbook Duo UX8406CA_UX8406CA - Geekbench

browser.geekbench.com

so roughly 5-6% higher perf/clock for PTL

And that’s at worst case.

 

[511]

WCL is RPL-U successor very nice i would say

https://twitter.com/x/status/1998452742130426005

RPL-U is 179mm2

https://twitter.com/x/status/1610278982154330113

 

[mikk]

Geekbench values are strongly impacted by memory speed. The faster DDR5 could account for a lot of the improvement. Unfortunately, neither memory speed nor power consumption are not listed in the link.

MT sure, ST not so much.

 

[mikk]

Indeed, but it might be the case that the comparison is apples to apples.

This would be on the high side favoring ARL:

ASUSTeK COMPUTER INC. ASUS Zenbook Duo UX8406CA_UX8406CA - Geekbench

Benchmark results for an ASUSTeK COMPUTER INC. ASUS Zenbook Duo UX8406CA_UX8406CA with an Intel Core Ultra 9 285H processor.

browser.geekbench.com

This is a cherry picked best score of 100 entries, I'm not sure if this a good comparison since we only have on entry from 388H. Most better scoring 285H devices are between 2800-2900 on Geekbench.

 

[jdubs03]

This is a cherry picked best score of 100 entries, I'm not sure if this a good comparison since we only have on entry from 388H. Most better scoring 285H devices are between 2800-2900 on Geekbench.

I did caveat my comment that it’s on the high side.

 

[dullard]

This is a cherry picked best score of 100 entries, I'm not sure if this a good comparison since we only have on entry from 388H. Most better scoring 285H devices are between 2800-2900 on Geekbench.

Geekbench 6 also lists the average score: 2604 ST and 14796 MT for the 285H. So, compared to the average 285H score, this 388H test is 17% (ST) to 19% (MT) faster. But, we have no idea if this is a good performing 388H or a bad performing one.

Intel Core Ultra 9 285H Benchmarks - Geekbench

browser.geekbench.com

 

[Magio]

Geekbench 6 also lists the average score: 2604 ST and 14796 MT for the 285H. So, compared to the average 285H score, this 388H test is 17% (ST) to 19% (MT) faster. But, we have no idea if this is a good performing 388H or a bad performing one.

Intel Core Ultra 9 285H Benchmarks - Geekbench

browser.geekbench.com

Average score isn't a good indicator because plenty of results are from people running the benchmark on power save mode (or on battery on laptops that throttle when unplugged).

So the average ends up being made up not just of silicon lottery variations but also just un representative results. Whereas this is may not be a prime 388h but it's still a representative score.

I do have to say, I hope Coyote Cove + N2(P) make for a return to form in ST, this is an OK score and probably an efficiency improvement but the gap to ARM cores is growing larger and larger.

 

[regen1]

WCL is RPL-U successor very nice i would say

https://twitter.com/x/status/1998452742130426005

RPL-U is 179mm2

https://twitter.com/x/status/1610278982154330113

WCL should be a very good chip overall esp. for internal cost-structure but it likely won't go for ultra-cheap price brackets ADL-N/Twin Lake were.
WCL-Refresh(4P+0E+4LPE) should be even better for performance. Even the cost-structures of MTL-U and ARL-U(aka MTL-U refreshed with Intel 3) with more tiles and advanced packaging aren't that great.

 

[511]

WCL should be a very good chip overall esp. for internal cost-structure but it likely won't go for ultra-cheap price brackets ADL-N/Twin Lake were.
WCL-Refresh(4P+0E+4LPE) should be even better for performance. Even the cost-structures of MTL-U and ARL-U(aka MTL-U refreshed with Intel 3) with more tiles and advanced packaging aren't that great.

Depends on the die size of WCL tbh but 2+4 should be better than 2+8 we are getting with RPL-U in PPA like lot better 3 Node Improvements.

 

[DavidC1]

I did caveat my comment that it’s on the high side.

Only peak scores without overclocking are relevant because that's the nature of user submitted benchmarks. That's why being able to easily arrange scores is so important.

Of course for Pantherlake it's early release, all the caveats apply, but since we don't know the extent of how far from a good configuration is, we can only do a general comparison. Sometimes we don't get full picture on the release date. I don't know why we are expecting anything near it now.

Default string Default string vs ASUSTeK COMPUTER INC. ASUS Zenbook Duo UX8406CA_UX8406CA - Geekbench

browser.geekbench.com

so roughly 5-6% higher perf/clock for PTL

This is pretty realistic and in line with their slides. Better than a Tick but not their generational 15-20% gain.

I do have to say, I hope Coyote Cove + N2(P) make for a return to form in ST, this is an OK score and probably an efficiency improvement but the gap to ARM cores is growing larger and larger.

I think only Arctic Wolf will show whether it can do this.

Just like Meteor/Arrow would show how Gelsinger's management would result in, and Clearwater Forest and Pantherlake would be the full culmination of it, Lip Bu Tan's equivalent would be starting with Novalake generation, and it would also show whether the E core team can keep up the impressive gains to actually have a chance to be a top industry core rather than just a blip on the radar for x86's excruciating slow decline.

 

[DavidC1]

Is there really a new category of "fans" of ARM vs x86? They are serving different markets ATM. They have went with different design choices.

Only because the bribery system(translation: lobbying in America) allowed laywers to protect x86 rather than blowing it wide open during AMD vs Intel lawsuits something like 40 years ago. Then we would have had x86 die long time ago replaced with ARM or everyone else would be on x86 including phones. Regardless there would be true competition rather than the moat they have created. Without that, Qualcomm for example would be a real threat as Intel/AMD would have to compete on performance and battery life alone. I don't believe what Intel/AMD is achieving with their cores is all that's possible with x86. They don't have true competition so we don't know the extent.

 

[regen1]

Depends on the die size of WCL tbh but 2+4 should be better than 2+8 we are getting with RPL-U in PPA like lot better 3 Node Improvements.

Better than RPL-U in those aspects, yes. WCL should be small(small 18A and N6 dies) and doesn't use advanced packaging. ADL-N and Twin Lake are pretty cheap as well and had the advantage of supporting DDR4 and DDR5. The ultra-cheap price points of ADL-N/Twin Lake SFF devices/Mini-PCS with memory and storage included might not be happen with WCL at its launch though eventually with time it can.

Just like Meteor/Arrow would show how Gelsinger's management would result in, and Clearwater Forest and Pantherlake would be the full culmination of it, Lip Bu Tan's equivalent would be starting with Novalake generation, and it would also show whether the E core team can keep up the impressive gains to actually have a chance to be a top industry core rather than just a blip on the radar for x86's excruciating slow decline.

CWF and PTL won't really be the end of it. First Tock-level Core u-arch under Gelsinger was Coyote Cove(NVL)/PantherCove-X(DMR). Unified Core started at least in 2024(if not earlier), this could be the first core-design to be majorly under Lip-Bu Tan's leadership.
Product execution wise(from core-concept/RTL to SoC implementation) there has been some or more level of overlap of tenures(GLC started under BK but by the time it got released in products(ADL and SPR) it was under Pat. Similarly LNC started under Swan).

 

[DavidC1]

Transmeta achieved 45nm Atom levels of perf/watt using a 90nm chip and needing a translation layer. I can't imagine what potentials the x86 world would have seen with true competition. I think the problem extends down to rest of the ecosystem, including companies like Dell, HP, and Lenovo, component vendors like Acer, Asus, and even ones like Foxconn.

Apple's iPhone basically forced the ecosystem to haul their bums or risk falling into irrelevancy.

CWF and PTL won't really be the end of it. First Tock-level Core u-arch under Gelsinger was Coyote Cove(NVL)/PantherCove-X(DMR). Unified Core started at least in 2024(if not earlier), this could be the first core-design to be majorly under Lip-Bu Tan's leadership.
Product execution wise(from core-concept/RTL to SoC implementation) there has been some or more level of overlap of tenures(GLC started under BK but by the time it got released in products(ADL and SPR) it was under Pat. Similarly LNC started under Swan).

He got in at early 2021. You can't say it isn't mostly under his leadership. Design by itself takes a year. Rest are basically making it physical and implementation plus testing. Raptorlake they claimed 3 years from design to availability on shelves.

CEOs aren't responsible for low level decisions. You can't anyway, there's just not enough time. If he was a chief architect it would be different. Making sure the company runs smoothly so products are made smoothly, those are his responsibilities.

 

[eek2121]

Only because the bribery system(translation: lobbying in America) allowed laywers to protect x86 rather than blowing it wide open during AMD vs Intel lawsuits something like 40 years ago. Then we would have had x86 die long time ago replaced with ARM or everyone else would be on x86 including phones. Regardless there would be true competition rather than the moat they have created. Without that, Qualcomm for example would be a real threat as Intel/AMD would have to compete on performance and battery life alone. I don't believe what Intel/AMD is achieving with their cores is all that's possible with x86. They don't have true competition so we don't know the extent.

You misunderstand and don’t give AMD and Intel enough credit as a result.

Current AMD/Intel chips are designed for scalable, high performance compute. ARM chips were designed for low power, mobile computing. Are there segments where they overlap? Sure, things like the Apple M series can reach desktop levels of performance. However, as they do that, efficiency begins to suffer and eventually the chip consumes just as much power as an Intel/AMD chip.

To put more simply: Every chip design has tradeoffs. AMD/Intel have chosen the things that matter to them the most, and ARM/Apple, Qualcomm have chosen the things that matter to them the most. For everyone, that is some combination of die size/efficiency/performance. It has little to do with the underlying architecture.

 

[DavidC1]

You misunderstand and don’t give AMD and Intel enough credit as a result.

Current AMD/Intel chips are designed for scalable, high performance compute. ARM chips were designed for low power, mobile computing. Are there segments where they overlap? Sure, things like the Apple M series can reach desktop levels of performance. However, as they do that, efficiency begins to suffer and eventually the chip consumes just as much power as an Intel/AMD chip.

Single thread the M5 beats the 285K and 9950X not by a small margin while achieving far lower power. I don't give them credit because it's not worthy of deserving it. It's way bigger of a difference than Netburst to Core 2 or Bulldozer to Ryzen. It's equal to multiple generations of that.

I can't emphasize how big of a difference it is. My system after enabling all the P and C-states the system was noticeably less responsive. Also desktop equivalents are ~5% faster than laptop variants, at the same rated clock. 3.5GHz Lion Cove on desktop is 5% faster than 3.5GHz on mobile, with the exact same dies. Yet the M5 is still faster. So the M5 scales just as well as AMD/Intel chips do. Because it can go from phones to high end laptops.

Can you imagine if the world was really one ISA? All x86 or all ARM? And why can't AMD make a platform competitive with Lunarlake? Or why can't both get their P cores to fit on Smartphones? Is it that it's impossible, or they aren't doing it? Do you know how much the pro-AMD or pro-Intel folks would shout if their chip had M5 levels of perf/watt? Then I will praise them.

 

[511]

Single thread the M5 beats the 285K and 9950X not by a small margin while achieving far lower power. I don't give them credit because it's not worthy of deserving it. It's way bigger of a difference than Netburst to Core 2 or Bulldozer to Ryzen. It's equal to multiple generations of that.

N3P vs N4P comparison really ? It's not bigger cause validation and backwards compatibility takes resourcing Apple doesn't give a damn about that AMD/Intel spent a lots of xtor on
SIMD no one seems to give a damm about it.

For example on N3E AMD Vector Units are like 0.78mm2 this is a very large area price to pay that people just ignore and move on.
Run SIMD code on Apple vs AMD and you will find it gets beaten in both power and perf/wattthe gap is not that big it's like 50% IPC in SPEC Int difference I remember Netburst vs Conroe being nearly double.

Can you imagine if the world was really one ISA? All x86 or all ARM? And why can't AMD make a platform competitive with Lunarlake? Or why can't both get their P cores to fit on Smartphones? Is it that it's impossible, or they aren't doing it? Do you know how much the pro-AMD or pro-Intel folks would shout if their chip had M5 levels of perf/watt? Then I will praise them.

Simple answer design target's AMD is optimizing for DC Intel (IDK about P cores) but E cores are focused on perf/area and perf/watt Apple is ST perf and perf/watt.

 

[MS_AT]

AMD/Intel spent a lots of xtor on
SIMD no one seems to give a damm about it.

I do. More than I care about Geekbench aggregate scores and Cinebench. I know, I will see myself out...

 

[Covfefe]

So the M5 scales just as well as AMD/Intel chips do. Because it can go from phones to high end laptops.

"Scalable high performance compute" is what eek said. Apple CPUs only have up to 32 cores. So no, Apple CPUs do not scale up as well as Intel's and AMD's.

 

[Geddagod]

and doesn't use advanced packaging.

Is it foveros still of emib? Higher bump pitch foveros?

Raptorlake they claimed 3 years from design to availability on shelves.

2.5 years. ADL was 3 years. RKL, IIRC, was 2 years? Could also have been 2.5.

However, as they do that, efficiency begins to suffer and eventually the chip consumes just as much power as an Intel/AMD chip.

Problem is that they don't.

To put more simply: Every chip design has tradeoffs.

But Apple is lowkey also just better.

For example on N3E AMD Vector Units are like 0.78mm2 this is a very large area price to pay that people just ignore and move on.

Things are so bad in x86 land that you can account for the FPU differences and still get really sad results.
Zen 5C in particular is a bad example of this. You can completely remove the FPU, getting an area of ~2.2mm2, which is only marginally smaller in area vs the Xiaomi X925 (2.56mm2), and is way larger than stuff like the mediatek x4 (1.5mm2).

Simple answer design target's AMD is optimizing for DC

ARM stuff would be better.

 

[adroc_thurston]

Is it foveros still of emib? Higher bump pitch foveros?

it's basic organtic laminate.
A very traditional CPU + PCH just with UCIe instead of OPIO.

Zen 5C in particular is a bad example of this. You can completely remove the FPU, getting an area of ~2.2mm2, which is only marginally smaller in area vs the Xiaomi X925 (2.56mm2), and is way larger than stuff like the mediatek x4 (1.5mm2).

dayum son x925 will never clock 3.7 in a DC env at 2W.

ARM stuff would be better.

in DC?
hahahahha hahahahahah hahahhahahaha hot damn this is funny.