Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[DrMrLordX]

When a brand new architecture based test chip comes back, how do they know that the bugs it is experiencing are from the architecture design flaws or the process?

You're getting pretty far into proprietary knowledge territory, though it should be pretty obvious. Defects often prevent the die from being functional at all, which is vastly different than having a design flaw/bug that may cause unexpected behavior. Parametric yield problems are probably caught during binning. It's appropriate to use a new design as a pipecleaner, and the practice is actually fairly common. Also look at Intel 3 (which admittedly, wasn't far off process-wise from Intel 4): Intel's first product on Intel 3 was Sierra Forest, not Arrow Lake-U (which was a direct port of Meteor Lake to Intel 3). A lot of that had to do with Intel needing to meet the specific demand of a valued customer, but even still, pushing you Arrow Lake-U early as a test chip would have made sense if the practice had any particular merit.

 

[igor_kavinski]

Also look at Intel 3 (which admittedly, wasn't far off process-wise from Intel 4): Intel's first product on Intel 3 was Sierra Forest, not Arrow Lake-U (which was a direct port of Meteor Lake to Intel 3). A lot of that had to do with Intel needing to meet the specific demand of a valued customer, but even still, pushing you Arrow Lake-U early as a test chip would have made sense if the practice had any particular merit.

Whose to say that ARL-U wasn't used to refine Intel 3 first and then put on the backburner while they turned their full attention to Sierra Forest?

 

[DrMrLordX]

Whose to say that ARL-U wasn't used to refine Intel 3 first and then put on the backburner while they turned their full attention to Sierra Forest?

It wasn't. Arrow Lake-U was on the backburner. It was launched later. Sierra Forest was a must-complete that had to be available to select customers by ~Apr 2024. Even Granite Rapids was officially launched before Arrow Lake-U.

 

[MoistOintment]

The point is to refine and improve 18A until it's ready for HVM (in other words, able to replace Intel 7, 4 and 3). Using a tried and tested older design helps them get there faster. Tick/tock cadence worked for them before because they tried not to chew too much by putting a new untested design on a brand new process. And now they are doing exactly that and the yields are in the gutter.

Completely different equipment used. Intel has DUV machines and needs usecases for them. It's just not financially feasible to shift your entire fab over to the last node - especially not when the latest node uses completely different lithography machines. TSMC certainly doesn't - you need to maintain volume on lower cost, legacy nodes. And until (if) Intel gets Intel 16 customers, Bartlett Lake on Intel 7 keeps those lines active that would otherwise sit idle. Intel 3 will also stay around for a while as well for non-leading edge use-cases. An external fabrication company needs to offer various nodes.

 

[regen1]

Intel Application Optimization: New Titles and Better Gaming Performance

Your system’s secret weapon just got stronger – Intel® Application Optimization (APO) is stepping up its game. With the latest update, Intel is expanding APO support to include 15 new game titles, delivering faster frame rates for smooth, immersive gaming. Whether you are exploring expansive...

community.intel.com

List of games:

Intel® Application Optimization List of Games

Shares a detailed list of games that may be optimized by Intel® Application Optimization.

www.intel.com

 

[Magio]

It's funny how I have so little expectations for PTL on the CPU side, but am still really excited about that 12 Xe³ SKU. Here's hoping that it's not limited to a few absurdly expensive designs and that it does well in reasonable thin and light TDPs.

 

[511]

It's funny how I have so little expectations for PTL on the CPU side, but am still really excited about that 12 Xe³ SKU. Here's hoping that it's not limited to a few absurdly expensive designs and that it does well in reasonable thin and light TDPs.

The CPU Part is interesting as well just not as Graphics it's just a node shrink of SKT/LNC with different core config so Efficiency is the only thing that improved for CPU.

 

[Magio]

The CPU Part is interesting as well just not as Graphics it's just a node shrink of SKT/LNC with different core config so Efficiency is the only thing that improved for CPU.

I mean low expectations as to performance improvements on the CPU side vs ARL. It seems like at best it will be a minimal improvement on that front, since it's the same core arch (basically) and clocks won't be much higher (if they even match ARL).

A 12Xe³ iGPU on the other hand is a very exciting prospect considering how well 8Xe²s already performed on LNL. Hopefully that doesn't end up bottlenecked by LPDDR5X bandwidth too much.

 

[511]

I mean low expectations as to performance improvements on the CPU side vs ARL. It seems like at best it will be a minimal improvement on that front, since it's the same core arch (basically) and clocks won't be much higher (if they even match ARL).

For peak performance yeah expect minimal gains but at lower power the gains should be pretty good.

A 12Xe³ iGPU on the other hand is a very exciting prospect considering how well 8Xe²s already performed on LNL. Hopefully that doesn't end up bottlenecked by LPDDR5X bandwidth too much.

It is though the memory speed is LPDDR5X 9600 max supported and it won't be enough to feed 12Xe3 and Xe3 is a major architecture change expect as big improvement as Xe2 was over Xe1.

 

[Magio]

It is though the memory speed is LPDDR5X 9600 max supported and it won't be enough to feed 12Xe3 and Xe3 is a major architecture change expect as big improvement as Xe2 was over Xe1.

Too bad LPDDR6 took a bit longer than initially expected to be ready. Would have been a boon for that iGPU.

 

[ToTTenTranz]

A 12Xe³ iGPU on the other hand is a very exciting prospect considering how well 8Xe²s already performed on LNL. Hopefully that doesn't end up bottlenecked by LPDDR5X bandwidth too much.

It is though the memory speed is LPDDR5X 9600 max supported and it won't be enough to feed 12Xe3 and Xe3 is a major architecture change.

Unlike the iGPUs in Lunar Lake and Arrow Lake, Panther Lake's iGPU is a client to the SoC's L3 cache with 18MB. The CPU cores also have plenty of L2, so if Intel plays this right, the iGPU should have plenty of effective memory bandwidth at lower resolutions.

 

[511]

Unlike the iGPUs in Lunar Lake and Arrow Lake, Panther Lake's iGPU is a client to the SoC's L3 cache with 18MB. The CPU cores also have plenty of L2, so if Intel plays this right, the iGPU should have plenty of effective memory bandwidth at lower resolutions.

First L3 is not shared with the CPU L3 afaik also the L2 is 16MB for 12Xe3 Cores.

 

[regen1]

Too bad LPDDR6 took a bit longer than initially expected to be ready. Would have been a boon for that iGPU.

12Xe3P(? or whatever they name it) IGPU in NVL series should be a decent upgrade over 12Xe3 of PTL but again would be limited by LPDDR5X speeds of the time.

 

[DavidC1]

12Xe3P(? or whatever they name it) IGPU in NVL series should be a decent upgrade over 12Xe3 of PTL but again would be limited by LPDDR5X speeds of the time.

These GPUs are low on the performance ladder and aren't that much affected by the bandwidth available. It's enough for them. It's the halo iGPUs like Iris and Strix Halo that matters. The architectural advancements that come new generation is enough to mitigate bottlenecks. Also for Intel they are in catchup mode since they are significantly behind in GPUs.

First L3 is not shared with the CPU L3 afaik also the L2 is 16MB for 12Xe3 Cores.

He's saying in PTL the CPU L3 is also shared by the GPU.

 

[LightningZ71]

Strix Point's iGPU begs to differ about being memory bandwidth limited. Despite being twice as large as Kraken's iGPU, it is FAR from being twice as fast.

 

[Josh128]

When a brand new architecture based test chip comes back, how do they know that the bugs it is experiencing are from the architecture design flaws or the process? Using an older design that they know hasn't got any design flaws helps them weed out the process issues much quicker.

As an analogy, does a person who changes one overclocking parameter at a time, extensively tests that and only moves to changing the next parameter find more success than someone who messes with multiple parameters in a single go? Obviously yes.

They test ~100+ chips from a wafer, if all of them have the same bug, its most likely to be architectural. They then run the problem code in software that emulates the transistor logic blocks that handle the code and go from there.

 

[igor_kavinski]

They test ~100+ chips from a wafer, if all of them have the same bug, its most likely to be architectural. They then run the problem code in software that emulates the transistor logic blocks that handle the code and go from there.

And then they find out from the software that no, it's the equipment. Some calibration issue. If they use the optical shrink though, they don't waste time checking the software because they know it has to be the process and it needs some tweaks etc.

 

[regen1]

These GPUs are low on the performance ladder and aren't that much affected by the bandwidth available. It's enough for them. It's the halo iGPUs like Iris and Strix Halo that matters. The architectural advancements that come new generation is enough to mitigate bottlenecks. Also for Intel they are in catchup mode since they are significantly behind in GPUs.

Well the various enhancements especially in compression techniques and increased L2 cache and B/W should certainly help but they would still likely be, in a number of scenarios, somewhat bottle-necked by bandwidth in gaming and compute

 

[adroc_thurston]

and aren't that much affected by the bandwidth available

yeah they are.

12Xe3P(? or whatever they name it) IGPU in NVL series should be a decent upgrade over 12Xe3 of PTL but again would be limited by LPDDR5X speeds of the time.

don' matter, it's gonna get roadkilled by the gfx13 blob either way.

 

[511]

yeah they are.

don' matter, it's gonna get roadkilled by the gfx13 blob either way.

No?

 

[adroc_thurston]

No?

Yeah.
PTL-H has a TTM advantage in shipping a 12/24 core config in premium GFX.
NVL-H has no such chance.

 

[511]

Yeah.
PTL-H has a TTM advantage in shipping a 12/24 core config in premium GFX.
NVL-H has no such chance.

NVL-H has Xe3P though Xe4 ain't coming before 27 anyways all the 128 bit SoC will be hampered by not having enough Mem Bandwidth either way.

 

[ToTTenTranz]

don' matter, it's gonna get roadkilled by the gfx13 blob either way.

Panther Lake H is releasing a year before Medusa Halo and Halo Mini / Premium.
With AMD pricing Strix Halo into no-one-picks-it-up oblivion, Strix Point is the one getting roadkilled by PTL-H.

And to be honest, Strix Point is already becoming a hard sell in iGPU territory. The 140V and 140T show similar performance in most games but get access to XeSS that allows for lower base render resolution for same IQ compared to FSR3. Panther Lake with larger Xe3 and access to L3 will seal the deal here.


The GFX13 line will have to compete with Nova Lake instead.

 

[Magio]

Panther Lake H is releasing a year before Medusa Halo and Halo Mini / Premium.
With AMD pricing Strix Halo into no-one-picks-it-up oblivion, Strix Point is the one getting roadkilled by PTL-H

And if Medusa Halo and Halo mini are positioned like Stryx Halo (so practically nothing uses them) and Medusa Point is the one that has to compete with PTL/NVL-H, then that's great for Intel iGPU wise considering Medusa Point will apparently stick with RDNA 3.5.

Battlemage is already competitive with that so if Celestial is a significant upgrade (or gets a new XeSS to compete with FSR4) then those 12Xe3 are going to make a meal out of anything RDNA 3.5.

 

[DrMrLordX]

And if Medusa Halo and Halo mini are positioned like Stryx Halo (so practically nothing uses them) and Medusa Point is the one that has to compete with PTL/NVL-H, then that's great for Intel iGPU wise considering Medusa Point will apparently stick with RDNA 3.5.

Battlemage is already competitive with that so if Celestial is a significant upgrade (or gets a new XeSS to compete with FSR4) then those 12Xe3 are going to make a meal out of anything RDNA 3.5.

The iGPU on Medusa Point won't matter for the majority of people buying it.