Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

Page 857 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.
Toggle sidebar Toggle sidebar
T

Tigerick

Senior member
Apr 1, 2022
846
799
106
Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

Intel Alder Lake - NIntel Wildcat LakeIntel Lunar LakeMediatek D9500
Launch DateQ1-2023Q2-2026 ?Q3-2024Q3-2025
ModelIntel N300?Core Ultra 7 268VDimensity 9500 5G
Dies2221
NodeIntel 7 + ?Intel 18-A + TSMC N6TSMC N3B + N6TSMC N3P
CPU8 E-cores2 P-core + 4 LP E-cores4 P-core + 4 LP E-coresC1 1+3+4
Threads8688
Max Clock3.8 GHz?5 GHz
L3 Cache6 MB?12 MB
TDP7 WFanless ?17 WFanless
Memory64-bit LPDDR5-480064-bit LPDDR5-6800 ?128-bit LPDDR5X-853364-bit LPDDR5X-10667
Size16 GB?32 GB24 GB ?
Bandwidth~ 55 GB/s136 GB/s85.6 GB/s
GPUUHD GraphicsArc 140VG1 Ultra
EU / Xe32 EU2 Xe8 Xe12
Max Clock1.25 GHz2 GHz
NPUNA18 TOPS48 TOPS100 TOPS ?






PPT1.jpg
PPT2.jpg
PPT3.jpg



As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



LNL-MX.png
 

Attachments

  • PantherLake.png
    PantherLake.png
    283.5 KB · Views: 24,028
  • LNL.png
    LNL.png
    881.8 KB · Views: 25,522
  • INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg
    INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg
    181.4 KB · Views: 72,430
  • Clockspeed.png
    Clockspeed.png
    611.8 KB · Views: 72,318
Last edited:
  • Like
Reactions: LaudaSur, jorden6655, john404 and 15 others
L

LightningZ71

Platinum Member
Mar 10, 2017
2,508
3,190
136
Which was my point.

AMD took a more performance base core with HT for their dense product. Even if the HT core only averages a 20+% MT uplift for the core, it's still giving you a ton more active threads. While individual VMs may only be provisioned with a few threads, they won't keep those threads fully populated with work either. In practice, those extra threads allow more active VMs without significantly degrading the performance of the others per rack unit (assuming no over provisioning is in use, but that also has some advantages for AMD as well).

The e cores for Intel should have had HT. Yes, cache per thread would have been an issue. There was an easy solution to that, dumping two of the P cores and doubling the L2 for the e cores. If the P cores had been bespoke for desktop and designed for maximum ST performance, those 6 cores would have given them all the ST performance they could have needed. Spreading the core out to 2+8+2+8+2 when viewed left to right would help isolate all the P cores hot spots better in low thread ST scenarios. You'd then have a 22/38 thread product competing against AMD's 16/32 product, likely absolutely pantsing them in MT performance while doing even better in ST as well.

It would have hurt their forest server products though, but they could have retained the smaller cache there and allowed the customer to decide on HT.
 
  • Like
Reactions: Tlh97
5

511

Diamond Member
Jul 12, 2024
4,523
4,144
106
LightningZ71 said:
AMD took a more performance base core with HT for their dense product. Even if the HT core only averages a 20+% MT uplift for the core, it's still giving you a ton more active threads. While individual VMs may only be provisioned with a few threads, they won't keep those threads fully populated with work either. In practice, those extra threads allow more active VMs without significantly degrading the performance of the others per rack unit (assuming no over provisioning is in use, but that also has some advantages for AMD as well).
Click to expand...
You need 2X the thread to gain 20% more Performance. I agree with the VM part though
 
L

LightningZ71

Platinum Member
Mar 10, 2017
2,508
3,190
136
192x1.2= ~238 core equivalents. How much faster is that C core than the competing Intel e core? We also have to take cache structure and performance into account too. All of this is excluding the full width AVX-512 in the V cores as well for those loads.

I don't doubt that, for a load that specifically is 288 threads, that doesn't use AVX-512, that the Intel E cores product will be faster. It's when you get to general compute where I have my doubts about the efficacy of the e core approach...
 
T

TheJudgeSarov

Junior Member
Oct 8, 2024
1
0
11
5

511

Diamond Member
Jul 12, 2024
4,523
4,144
106
LightningZ71 said:
I don't doubt that, for a load that specifically is 288 threads, that doesn't use AVX-512, that the Intel E cores product will be faster. It's when you get to general compute where I have my doubts about the efficacy of the e core approach...
Click to expand...
General purpose compute is not AVX-512
 
L

LightningZ71

Platinum Member
Mar 10, 2017
2,508
3,190
136
When you are hosting VMs for external customers, they can run anything on it, including AVX512 loads. That's what I mean by general purpose.
 
  • Like
Reactions: 511
Covfefe

Covfefe

Member
Jul 23, 2025
44
63
51
TheJudgeSarov said:
Hybrid Cores is coming


EP4579444A1 - Software defined super cores - Google Patents

Techniques for software defined super core usage are described. In some examples, a fist and second processor core are to operate as a single virtual core enabled by the operating system to fetch the first set of instruction segments of the single threaded program and the second set of...
patents.google.com
Click to expand...
Fwiw, Ian Cutress says this is nothing.

https://old.reddit.com/r/intel/comments/1n33e3u/intel_patent_software_defined_super_cores/nbhybr7/

Intel acquired Soft Machines in 2016, who pioneered the concept of VISC which people called 'reverse hyperthreading'. Some idiots threw speculation that SkyLake would have it, but idiots being idiots. It's since been a quiet research project and/or mothballed internally.
Click to expand...
 
  • Like
Reactions: Thunder 57
O

OneEng2

Senior member
Sep 19, 2022
840
1,105
106
LightningZ71 said:
192x1.2= ~238 core equivalents. How much faster is that C core than the competing Intel e core? We also have to take cache structure and performance into account too. All of this is excluding the full width AVX-512 in the V cores as well for those loads.

I don't doubt that, for a load that specifically is 288 threads, that doesn't use AVX-512, that the Intel E cores product will be faster. It's when you get to general compute where I have my doubts about the efficacy of the e core approach...
Click to expand...
for highly treaded DC usage (CWF's main usage), SMT gives much more like 1.4x-1.5x in general. At 1.4x using a 256c/512t Zen6c Venice D as competition, Venice D would be the equivalent of 358 CWF cores.... if it was AVX512 enhanced code, then more than that.

My point is that CWF (by the latest rumor) will launch in 2026 .... as will Venice D. I suppose months matter, but Intel leaving out SMT from the design is going to cripple them IMO.

Additionally, Venice D will have more bandwidth (1.6Tb/sec vs 1.3Tb/sec).

I do think that Intel will release CWF prior to AMD releasing Venice D, but I am wondering how much volume they will be able to produce before they face the Venice D competition?
 
  • Like
Reactions: Tlh97
L

LightningZ71

Platinum Member
Mar 10, 2017
2,508
3,190
136
OneEng2 said:
for highly treaded DC usage (CWF's main usage), SMT gives much more like 1.4x-1.5x in general. At 1.4x using a 256c/512t Zen6c Venice D as competition, Venice D would be the equivalent of 358 CWF cores.... if it was AVX512 enhanced code, then more than that.

My point is that CWF (by the latest rumor) will launch in 2026 .... as will Venice D. I suppose months matter, but Intel leaving out SMT from the design is going to cripple them IMO.

Additionally, Venice D will have more bandwidth (1.6Tb/sec vs 1.3Tb/sec).

I do think that Intel will release CWF prior to AMD releasing Venice D, but I am wondering how much volume they will be able to produce before they face the Venice D competition?
Click to expand...
Their largest customers will have samples of both vendor's parts long before release day...
 
O

OneEng2

Senior member
Sep 19, 2022
840
1,105
106
And I am thinking that leaks should be a prelude to any release because of that 😁.

So far there has been nothing of consequence leaked on Intel or AMD.
 
J

Joe NYC

Diamond Member
Jun 26, 2021
3,647
5,186
136
fastandfurious6 said:
Yeah it will be 100% eaten by zen6. Time would be their advantage

When leaks for ptl and zen6? Hmm
Click to expand...

In mobile too? We don't know anything about the first mobile Zen 6 products to be launched and when. Only about RDNA5 based Zen 6 that will be probably 1 year behind PTL to market.

There should be the Gorgon Point CPUs in the meantime, which will initially be the competition for PTL from AMD side, and these are still Zen 5.
 
L

LightningZ71

Platinum Member
Mar 10, 2017
2,508
3,190
136
I think we'll all be surprised if Gorgon Point is anything more involved than the Phoenix Point to Hawk Point transition.
 
5

511

Diamond Member
Jul 12, 2024
4,523
4,144
106
Joe NYC said:
In mobile too? We don't know anything about the first mobile Zen 6 products to be launched and when. Only about RDNA5 based Zen 6 that will be probably 1 year behind PTL to market.

There should be the Gorgon Point CPUs in the meantime, which will initially be the competition for PTL from AMD side, and these are still Zen 5.
Click to expand...
He is dreaming PTL is scheduled to launch before Zen 6 and by Zen 6 Launch it will be in High Volume and Zen6 will barely have any volume.
 
  • Like
Reactions: DKR
adroc_thurston

adroc_thurston

Diamond Member
Jul 2, 2023
7,094
9,850
106
511 said:
It's even more PITA for cooling 🤣
Click to expand...
Cooling is fine, hybrid bonded stacks are fine thermals-wise (see MI300X/A/yaddayadda. Or fat full-frame tri-stack sensors from Sony).
Yields, OTOH, are hard.
Frankly, they should've kept BSPDN as optionality for 18A.
 
You must log in or register to reply here.

TRENDING THREADS

COMPANY
RESOURCES
FOLLOW
Top Bottom