Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+4+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[DavidC1]

I would guess that if the e-core only CPU is real, it's a low end model like the i3-N305. Maybe they add 4-lpe cores on top of the 8 e-cores.

Why would it be a low end if it's a Xeon and they are already not bothering to create a separate Skymont successor to N305?

Gracemont: Per clock Integer performance with a P core 2 gen ago
Skymont: Per clock Integer and FP performance with last gen P core
Arctic Wolf: I would not be surprised if it is on par with last gen P core in absolute performance

So am I calculating this correctly? I see the IPC of the P cores (2290/1685)raw score / (5.7/4.6)clockspeed margin or only about 10% IPC margin for the P
cores?

Yes, but didn't we know that already?

Clockspeed scales at ~90% on Cinebench so it's about 12%.

 

[GTracing]

Why would it be a low end if it's a Xeon and they are already not bothering to create a separate Skymont successor to N305?

Gracemont: Per clock Integer performance with a P core 2 gen ago
Skymont: Per clock Integer and FP performance with last gen P core
Arctic Wolf: I would not be surprised if it is on par with last gen P core in absolute performance

The way I read it initially, the e-core part would be consumer; they said it was a nova lake part, and server parts of have different codenames. Though looking at the tweet again, I'm not sure if that's what they meant.

If it is Xeon, then I think you're right that it wouldn't be low end.

 

[LightningZ71]

They could take an Arrow Lake package and just drop a special core chiplet on it with 32-40 e-cores to maximize MT throughput.

I would Imagine that they would want more PCIe lanes and 2 more DDR channels

 

[511]

I hope we get a triple channel platform it's time to move on from Dual channel.
it's fine if only some motherboard have it but the CPU supporting it is mandatory

 

[Harry_Wild]

Has Intel released a mobile CPU without a fan inside to compete with Apple's Air and Qualcomm's Windows mobile CPU?

 

[511]

Has Intel released a mobile CPU without a fan inside to compete with Apple's Air and Qualcomm's Windows mobile CPU?

LNL is fanless capable but no one did it

 

[DavidC1]

LNL is fanless capable but no one did it

Fanless has lots of advantages from my own experience.
-Lower heat, since the system needs to be able to handle not needing a fan
-Battery longevity, because of the lower heat. I bought it used and few years since then but the degradation is still only in the 10-15% range.
-Even lower power because it doesn't need to power the fan.
-No worry about dust because it doesn't have vents.

I hope we get a triple channel platform it's time to move on from Dual channel.

We already have HEDT and the extra channel is a waste for vast majority of systems, while permanently increasing the cost.

 

[MS_AT]

We already have HEDT and the extra channel is a waste for vast majority of systems, while permanently increasing the cost.

When you are building something general purpose then something will end up unused. The system needing more mem channels might not need so much PCIe, or the system with big PCIe requirements might not need mem channels or the sheer amount of cores hedt brings.

But is the alternative of custom building everything more preferable when you will loose economy of scale? Probably for the hyperscalers as they can make up the neccessary volume on their own, but for small scale deployments you probably get short end of the stick either way

 

[511]

Fanless has lots of advantages from my own experience.
-Lower heat, since the system needs to be able to handle not needing a fan
-Battery longevity, because of the lower heat. I bought it used and few years since then but the degradation is still only in the 10-15% range.
-Even lower power because it doesn't need to power the fan.
-No worry about dust because it doesn't have vents.

We already have HEDT and the extra channel is a waste for vast majority of systems, while permanently increasing the cost.

Yes but 1 extra channel will be needed with this ridiculous core count increase

 

[igor_kavinski]

Maybe with PCIe 6.0, they can create a pluggable DIMM, SODIMM or CAMM2 module that users can just swap in or out based on their needs. Sell mobos cheap without RAM support then user buys the appropriate channel pluggable module based on their needs (single channel for office PCs, dual channel for power users, triple channel for enthusiasts and so on).

 

[LightningZ71]

DDR6 brings roughly double the data transfer rate of DDR5, which doubled what DDR4 had. The regular dual "channel" AM6 socket should have similar memory bandwidth to the ZEN2 EPYC servers, which topped out at 8 channels of DDR4 (edited: I originally said DDR5) and 32 cores with less L2 cache per core and likely far less L3 cache per core.

I think there is enough memory bandwidth for consumer platforms.

What I personally want more of is PCIe bandwidth. I want 16 lanes of PCIe 6 for the video card, 8 x PCIe 6 lanes for the system IO controller, and a pair of PCIe 5.0 x4 m.2 sets for SSDs or other motherboard needs. This way, creator or semi pro boards can offer three additional full length slots for extra video cards, storage cards, or specialized I/O cards. It's going to be a VERY long time before there are a lot of PCIe 6, or even 5 cards out there, however, there are many 4.0 and 3.0 cards out there that appreciate having all 16 lanes. All that can come from the IO controller if it's fed with 8 x 6.0 lanes.

 

[511]

Maybe with PCIe 6.0, they can create a pluggable DIMM, SODIMM or CAMM2 module that users can just swap in or out based on their needs. Sell mobos cheap without RAM support then user buys the appropriate channel pluggable module based on their needs (single channel for office PCs, dual channel for power users, triple channel for enthusiasts and so on).

Intel already has a patent like that For GPUs you can upgrade VRAM on GPU

 

[MS_AT]

What I personally want more of is PCIe bandwidth.

More BW or more lanes? I mean 16 PCIe 5 lanes could be plenty if we had sensible options to bifurcate the lanes. You could put 8 lanes to gpu and use the rest for 4x nvme drives /mix and match with network controllers and have sufficient BW (at PCIe 4.0 rate).

 

[511]

If I had to pick one more lanes not bandwidth .

There is nothing on consumer side needing that needs that much bandwidth more lanes yes

 

[DrMrLordX]

So am I calculating this correctly? I see the IPC of the P cores (2290/1685)raw score / (5.7/4.6)clockspeed margin or only about 10% IPC margin for the P cores?

Yes, but as we all should know by now, low-clockspeed designs can scale better. Without normalizing for clockspeed, the P core is roughly 35% faster, showing that Atom has a ways to go before it can supplant P cores entirely. Intel would be in a much stronger position if they could replace 5.5-6 GHz Core with ~4.5 GHz Atom.

 

[zir_blazer]

Maybe with PCIe 6.0, they can create a pluggable DIMM, SODIMM or CAMM2 module that users can just swap in or out based on their needs. Sell mobos cheap without RAM support then user buys the appropriate channel pluggable module based on their needs (single channel for office PCs, dual channel for power users, triple channel for enthusiasts and so on).

You are literally describing CXL when used with RAM.

 

[Thibsie]

Intel already has a patent like that For GPUs you can upgrade VRAM on GPU

Back to S3 Trio 64V+ era

 

[DavidC1]

Yes but 1 extra channel will be needed with this ridiculous core count increase

Not really. Performance has been limited by power for over a decade now. They won't get twice the power headroom. If it's 30% faster than it only needs 30% more bandwidth.

 

[LightningZ71]

More BW or more lanes? I mean 16 PCIe 5 lanes could be plenty if we had sensible options to bifurcate the lanes. You could put 8 lanes to gpu and use the rest for 4x nvme drives /mix and match with network controllers and have sufficient BW (at PCIe 4.0 rate).

Essentially, more lanes = more bandwidth, but, yes, more end user available lanes...

 

[LightningZ71]

Intel already has a patent like that For GPUs you can upgrade VRAM on GPU

This takes me back to my first "performance" video card, a VL Bus ATI Mach32 card that shipped with 1MB of RAM with actual edge sockets for an additional 1MB of VRAM, which I dutifully added once I could afford it.

 

[LightningZ71]

If I had to pick one more lanes not bandwidth .

There is nothing on consumer side needing that needs that much bandwidth more lanes yes

Going from AM5 to AM6, I do want more lanes; 4 of them. I want to double the lane count to the board IO Die to 8, and upgrade it to PCIe 6. That would quadruple the bandwidth to it and allow all sorts of multiplexing of downstream lanes.

 

[MS_AT]

Essentially, more lanes = more bandwidth, but, yes, more end user available lanes...

Sure, but on consumer platforms, we end up getting more BW, while the lane counts stay the same. Using multiplexing chips in theory you could add cards that would turn 1 PCIe 5.0 x8 to 4 links of PCIe 4.0 x4 but these are rather expensive, so having more lanes from the CPU even if older gen seems like a better deal for the end user if bifurcation options are exposed in bios. Then you could turn 1 PCIe 4.0 x16 into 4 links of PCIe 4.0 x4 with passive add-on card. Or manufacturers could go Samsung way and support PCIe 5.0 x2 and PCIe 4.0 x4 at the same time like in their latest evo drive.

 

[LightningZ71]

The IOD on the motherboard is already a multiplexer. The USB root hubs, the Ethernet MACs, the serial IO hub, ancillary stuff, it's all internally just PCIe devices. They even expose a few external lanes already. Nothing beyond the primary video card is heavily latency sensitive, they just need bandwidth in the form of PCIe lanes. The more lanes, the better, as lots of older but valuable cards are wide PCIe 3 implementations.

 

[Kepler_L2]

Going from AM5 to AM6, I do want more lanes; 4 of them. I want to double the lane count to the board IO Die to 8, and upgrade it to PCIe 6. That would quadruple the bandwidth to it and allow all sorts of multiplexing of downstream lanes.

8x actually, current link is PCIe Gen4

 

[poke01]

(I will no longer be posting X links, only screenshots.)



PTL P core is average. 18A good.