Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+4+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[GTracing]

So of the 3-tiered cores, we have Coyote Cove for P-Cores, Arctic Wolf for E-Cores, and there are also the LP-Cores... Are these rumored to also be Arctic wolf derived and sit separately on the SoC tile as with Lunar and Arrow Lake?

Yes, they are most likely Artic Wolf.

Small correction, but Lunar Lake doesn't have an SoC tile like Arrow Lake. It has the CPU cores, iGPU, and memory controller all on one tile. Panther Lake and Nova Lake are rumored to be like Lunar Lake, but with the iGPU on a separate tile.

 

[igor_kavinski]

there are also the LP-Cores... Are these rumored to also be Arctic wolf derived and sit separately on the SoC tile as with Lunar and Arrow Lake?

Not sure. Arrow Lake doesn't have LP cores. And Lunar Lake's LP cores are Skymonts (maybe power optimized ones and slightly better than the Arrow Lake ones).

 

[511]

So of the 3-tiered cores, we have Coyote Cove for P-Cores, Arctic Wolf for E-Cores, and there are also the LP-Cores... Are these rumored to also be Arctic wolf derived and sit separately on the SoC tile as with Lunar and Arrow Lake?

I doubt they would enable those cores they would just bin the one or disable those for desktop the only reason we are getting this is they are expanding chiplets to entire portfolio for Clients Common SOC+Varied iGPU+ Compute Tile

 

[oak8292]

If Intel spent 20Bn on GAA with BSPDN, how much do you think it will cost to do CFET with buried power via? It is my understanding that the CFET process will add as many process steps over GAA as GAA did beyond FinFET. Another 20Bn?

The alure of 2x density is a powerful draw though. From what I can read now, it looks like 2030+ for this technology.

If BSPDN and GAA have heat removal issues then one can only imagine the problems with stacking transistors and using back side power delivery. The power reduction needs to keep up with transistor density. It seems to me that frequency reductions will be required for CFETs and these transistors may not be used for P cores as IPC isn’t going to keep improving fast enough.

P core die may hold on a transistor specifically optimized for frequency.

 

[dullard]

Arrow Lake doesn't have LP cores.

Arrow Lake-H and Arrow Lake-U both have LP-E cores. They reuse the Meteor Lake SoC tile which includes them. Meaning the Arrow Lake LP-E cores are on a fairly ancient node (TSMC N6). From what I gather, the intention of a very low power but usable state just doesn't quite pan out with those LP-E cores. They are too underpowered for most use cases. Video playback is an exception with reviews getting ~23 hours on a big battery. https://hothardware.com/reviews/intel-arrow-lake-h-laptop-platform-review?page=3 and https://infogram.com/1ppln0nxjed60earw3xk5vzvndaz70eke1q

However with Nova Lake's rumored 4 LP-E cores and moving to Intel 18A, the Nova Lake's LP-E cores should theoretically be much more practical for many other use cases.

 

[igor_kavinski]

Arrow Lake-H and Arrow Lake-U both have LP-E cores.

1 GHz frequency. Sounds like a dream come true for 80s/90s era retro gamers. Peg DOSBox or similar emulator to LP E-core and solve the issue of old games running too fast.

 

[511]

1 GHz frequency. Sounds like a dream come true for 80s/90s era retro gamers. Peg DOSBox or similar emulator to LP E-core and solve the issue of old games running too fast.

Naa it's 2.2 GHz boost 1Ghz is idle frequency they should have added 4 LP-E Crestmont core.
They took untill LNL to fix it meaning they identified it in the next iteration

 

[OneEng2]

If BSPDN and GAA have heat removal issues then one can only imagine the problems with stacking transistors and using back side power delivery. The power reduction needs to keep up with transistor density. It seems to me that frequency reductions will be required for CFETs and these transistors may not be used for P cores as IPC isn’t going to keep improving fast enough.

P core die may hold on a transistor specifically optimized for frequency.

Certainly a valid concern. BSPDN heat removal is because the chip isn't directly in contact with the heat sink any more. From what I have heard, this results in localized areas where power density builds up or "hot spots" in the design. If you than at CFET on top of that where essentially another layer of insulation separates a heat producing element from the heat sink, then you would be correct. The power removal issue gets worse.

Additionally, while I agree that raising transistor density x2 is a great thing for a design as everything can be made better, wider, deeper, more sophisticated, etc, it also doubles the heat density.

I guess we should get past BSPDN first to see if reality follows theory here .

 

[Hitman928]

Certainly a valid concern. BSPDN heat removal is because the chip isn't directly in contact with the heat sink any more. From what I have heard, this results in localized areas where power density builds up or "hot spots" in the design. If you than at CFET on top of that where essentially another layer of insulation separates a heat producing element from the heat sink, then you would be correct. The power removal issue gets worse.

Additionally, while I agree that raising transistor density x2 is a great thing for a design as everything can be made better, wider, deeper, more sophisticated, etc, it also doubles the heat density.

I guess we should get past BSPDN first to see if reality follows theory here .

It's not about being directly in contact (most chips today aren't and even when they are, there are still thermal resistive layers involved), it's about the chip not being upside down anymore and the substrate being excessively thinned. Currently, chips are flipped upside down with the bottom facing up towards the heatsink. This is great for better connections to the board (bumps instead of bond wires) and better thermal conductivity as the hottest part of the chip is surrounded by "thick" silicon which spreads out the heat and conducts it rather effectively towards the heatsink. With BSPD, the silicon is comparatively very thin and so it loses much of its ability to spread the heat out before hitting an area of higher thermal resistance. Additionally, the silicon now faces towards the socket rather than the heatsink, so the heat has to pass through a higher thermal resistive area to reach the heatsink than it did without BSPD.

 

[511]

Skymont carrying hard ARL

Intel Arrow Lake-H CPU analysis: Core Ultra 200H makes Lunar Lake almost redundant

Notebookcheck analysis of the new Intel Core Ultra 9 285H of the Arrow Lake generation.

www.notebookcheck.net

 

[511]

Finally Intel listening to consumers

https://twitter.com/x/status/1890043216558526535

 

[Markfw]

Finally Intel listening to consumers

https://twitter.com/x/status/1890043216558526535

does it have avx-512 ?

 

[511]

does it have avx-512 ?

It has AVX 10.2/256 so you would get all the ISA featurea of AVX-512 but at 256 bit vectors

 

[Markfw]

It has AVX 10.2/256 so you would get all the ISA featurea of AVX-512 but at 256 bit vectors

So at half the speed of Zen 5 and the same on Intel servers ?

 

[511]

So at half the speed of Zen 5 and the same on Intel servers ?

Regarding the speed I am not sure the vectors are half the sure but I can't say anything unless we see it in action.

As for Intel servers E cores will get the 256 bit vector and P will get the 512 bit vectors

 

[Markfw]

Regarding the speed I am not sure the vectors are half the sure but I can't say anything unless we see it in action.

As for Intel servers E cores will get the 256 bit vector and P will get the 512 bit vectors

I am only going based on what Zen 4 with 256 bit does compared to Zen 5 (avx-512 code only) and its close to half the performance with 256 bit.

 

[511]

I am only going based on what Zen 4 with 256 bit does compared to Zen 5 (avx-512 code only) and its close to half the performance with 256 bit.

It was due to the fact that they were double pumping 256 bit to do AVX-512 there will be no double pumping here since they will support 256 bit vectors natively.

 

[igor_kavinski]

Finally Intel listening to consumers

https://twitter.com/x/status/1890043216558526535

Important question: How many E-cores?

 

[Markfw]

Important question: How many E-cores?

Yes, I agree. I would think that all the E-core nonsense would have been a message to get rid of them.

 

[LightningZ71]

I'm going to go out on a limb and say that the number of E cores will be a multiple of 4!

 

[GTracing]

I would guess that if the e-core only CPU is real, it's a low end model like the i3-N305. Maybe they add 4-lpe cores on top of the 8 e-cores.

 

[511]

Important question: How many E-cores?

32 if they bin correctly

 

[511]

Panther lake should be good if they dropped the PL2 to 64W max and even the worst limit is 80W

 

[511]

Finally someone did E Core vs P core and it's ...

https://twitter.com/x/status/1890405515517390896

E core

P core

 

[ondma]

So am I calculating this correctly? I see the IPC of the P cores (2290/1685)raw score / (5.7/4.6)clockspeed margin or only about 10% IPC margin for the P cores?
Edit: This is based on the single core values.

It comes out the same if you use the multicore score:
P core = 17463/8 = 2183 per core
E core = 25728/16 = 1608 per core
IPC ratio = (2183/1608) / (5.7/4.6) = 1.36/1.24 = 1.10
Of course the real performance difference is still 36% more for P core, since the E cores cant match the clockspeed.

I wonder what the power consumption is for 8P vs 16E?