Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Gideon]

IMO the biggest thing Intel needs to improve is the L3 latency (on top of the memory latency, they seem to be at) which is 80% higher than on HX 370.

TSMC救不了Intel：酷睿Ultra 7 255H（Arrow Lake H45）测试 | David Huang's Blog

At the 8 MB test point, the delay of 255H reaches 75 cycles, close to the 81-cycle of 155H, which is much higher than the 59 cycle of 258V and the 45 cycle of HX 370. Although the 255H has much more L3 capacity than the HX 370, its access to the L3 is 80% more expensive than the HX 370

not holding my breath though ...

 

[Geddagod]

IMO the biggest thing Intel needs to improve is the L3 latency (on top of the memory latency, they seem to be at) which is 80% higher than on HX 370.

TSMC救不了Intel：酷睿Ultra 7 255H（Arrow Lake H45）测试 | David Huang's Blog

not holding my breath though ...

What's the Zen 5 DT L3 latency in cycles again?
Tell me if I'm tripping, but didn't Phoenix have the same L3 latency in cycles as DT Zen 4 did, despite having like half the L3 cache?

 

[inquiss]

2025 is going to be another MEH year for x86 CPUs

Halo is a very fun part

 

[511]

Intel has not had a "tick" core uplift that large since like, when? Idk. I find it super hard to believe

Only for P cores last was tiger lake when the P core(Willow Cove) Tick had 5-7% IPC Improvement.

Crestmont had 5% IPC Increase btw

 

[GTracing]

IMO the biggest thing Intel needs to improve is the L3 latency (on top of the memory latency, they seem to be at) which is 80% higher than on HX 370.

TSMC救不了Intel：酷睿Ultra 7 255H（Arrow Lake H45）测试 | David Huang's Blog

not holding my breath though ...

Lion Cove does have a larger L2 and an extra L1.5 cache. Those differences increase the L3 latency but reduce the performance impact from the higher latency.

AMD's cache setup is definitely better overall, but that 80% isn't apples to apples.

 

[Geddagod]

I really do wish there were some reviews that tested "CCX" power of AMD and Intel chips too for 1T and nT benchmarks. Considering Intel's much slower L3, and also larger core private caches, I suspect this would shift the power curve slightly more in Intel's advantage, though I suspect AMD would still have a large advantage despite that.

Only for P cores last was tiger lake when the P core(Willow Cove) Tick had 5-7% IPC Improvement.

Crestmont had 5% IPC Increase btw

IIRC WLC was actually a slight regression in P-core IPC vs SNC in mobile chips from Anandtech's testing.
Idk about crestmont tho I think raichu tested it but im on campus and im sooo embarrassed to check raichus testing since opening his twitter account would be.... uhh.... interesting lol

 

[igor_kavinski]

Halo is a very fun part

Strix Halo? We find out for sure tomorrow. Or referring to some future 2025 Intel Halo part?

 

[511]

I really do wish there were some reviews that tested "CCX" power of AMD and Intel chips too for 1T and nT benchmarks. Considering Intel's much slower L3, and also larger core private caches, I suspect this would shift the power curve slightly more in Intel's advantage, though I suspect AMD would still have a large advantage despite that.

IIRC WLC was actually a slight regression in P-core IPC vs SNC in mobile chips from Anandtech's testing.
Idk about crestmont tho I think raichu tested it but im on campus and im sooo embarrassed to check raichus testing since opening his twitter account would be.... uhh.... interesting lol

Yeah definitely I can understand don't want to see cosplaying images on campus

 

[poke01]

Strix Halo? We find out for sure tomorrow. Or referring to some future 2025 Intel Halo part?

It’s Strix halo. Intel isn’t releasing a huge part in 2025

 

[Geddagod]

It’s Strix halo. Intel isn’t releasing a huge part in 2025

Lowkey PTL might be interesting for the iGPU alone lol. It would be soooo funny tho if it still cant compete in nT perf/watt with 12C strix.

 

[OneEng2]

https://twitter.com/x/status/1890974437337428301

So 18A is a bit more dense vs N3B nice all the people saying 18A is not good should be in shambles

Not much more dense, thus my current reservations about 18A CPU's having significant IPC improvements over N3B parts.

They have to prove that they can do it. And if they do? Then are you going to give them some credit? Based on publicly available information, 18A will be competitive if not ahead in shipping products.

If 18A performs well and yields well and the process doesn't cost Intel an arm and a leg to utilize, then yes, it will be worth HUGE credit to Intel.

Intel will have brought GAA, BSPDN, and a completely different transistor library to the market and made themselves competitive (eventually) after they pay off the NRE for the R&D done to get 18A going. This is nothing to belittle ..... if it happens that way.

I suppose lots of us are remembering much lower risk processes being botched at Intel recently. 18A seems full of risk to me.

 

[Geddagod]

Not much more dense, thus my current reservations about 18A CPU's having significant IPC improvements over N3B parts.

Is LNC too "wide" of a core for N3 though? Zen 5 is built on a N5 class node, with better perf/watt than LNC across the curve. I think they could get another tock out of 18A without shifting the perf/watt curve too much to the upper right and have a regression at lower power (cough RKL cough). If they fix their physical design too.

 

[Ghostsonplanets]

process doesn't cost Intel an arm and a leg to utilize, then yes, it will be worth HUGE credit to Intel.

Considering Intel has said in the past that Intel 7 is quite more expensive for them than Intel 4/3, I don't see 18A costing an arm and leg. Specially given High-NA was postponed to 14A.

The fact Intel will replace their Intel 7 Raptor Lake mainstream designs with 18A based Wildcat Lake is an indication for me that 18A process costs should be very healthy for their margins.

 

[LightningZ71]

If Intel 3 was that much less expensive than Intel 7, it would have made sense to release a mobile version of Raptor Lake on Intel 3 instead of the mess that Meteor Lake is. It's not like they didn't already mostly port the Raptor Cove and Crestmont cores over to that IP already.

 

[jdubs03]

If 18A performs well and yields well and the process doesn't cost Intel an arm and a leg to utilize, then yes, it will be worth HUGE credit to Intel.

Intel will have brought GAA, BSPDN, and a completely different transistor library to the market and made themselves competitive (eventually) after they pay off the NRE for the R&D done to get 18A going. This is nothing to belittle ..... if it happens that way.

I suppose lots of us are remembering much lower risk processes being botched at Intel recently. 18A seems full of risk to me.

Fair enough. To me though it just seems like a good bit of wish-casting for chapter 11 bankruptcy or a fire sale. It’s not helpful if that were to happen.
We shouldn’t be hoping for a TSMC monopoly.

 

[OneEng2]

Fair enough. To me though it just seems like a good bit of wish-casting for chapter 11 bankruptcy or a fire sale. It’s not helpful if that were to happen.
We shouldn’t be hoping for a TSMC monopoly.

Not hoping for anything other than a great 18A release for exactly the reasons you stipulate! My gut tells me that if 18A were really doing as good as leaks (and Intel) claim, there would be a great deal more enthusiasm for Intel to keep its CEO that created the strategy that got it there.

Additionally, I remember all the hype from Samsung's 3nm GAA process that ended up being a big disappointment. The recent news that Intel was delaying CWF is also not that promising.

My fear for Intel is that they have been, and remain in, denial that they can wish themselves back into a dominant position using the same strategy that worked for them in the past. The big problem being, physics and economics are not like they were in the past .... so this strategy no longer works.

BSPDN should also be providing a good deal more effective transistor density. IIRC, an additional 30% simply by allowing more compressed layout options with fewer vias to interrupt logic density. They don't seem to be advertising this at all though, so I am a little concerned on that front as well. Perhaps Intel has de-risked some of the problems with BSPDN by giving up on this theoretical density improvement? I have also heard that traditionally, BSPDN suffers from hot spots in the die (at least much more so than current FinFET designs do). Shouldn't be a problem for Panther Lake and CWF where it is unlikely that they will need to clock cores to max frequency, but in Nova Lake, this could become a big issue.

Where I have the MOST hope for Intel, is in an improved IOD and a core design that can greatly reduce the latency ARL currently suffers from. Seems like this would really open up the architecture.

Strange. Intel always had the highest transistor density processes, and lowest latency cache ....... once upon a time.

 

[DavidC1]

I highly doubt the P-cores get that large of an uplift. I don't even think the P-cores will get a greater gain than the E-cores. At best I think uncore changes might net decent IPC gains in some applications, but other than that....

I'd like to believe that they are doing two middle of the road gains in a row rather than 0% on one year and 20% a later later.

Plus if Cougar Cove gets nothing it starts getting real bad for P cores real quick, especially if the P core successor to Panther Lake is getting only 8-10% again. That means Arctic Wolf may potentially only be ~10% behind the P core including the clock differences, why have them at all then?

Current Lion + Sky may be akin to Prescott + Yonah. What you are saying may be something like Tejas + Conroe.

Only for P cores last was tiger lake when the P core(Willow Cove) Tick had 5-7% IPC Improvement.

Crestmont had 5% IPC Increase btw

What? Where did you get those numbers? Crestmont got 3-5%. Willow Cove regressed at worst and equal at best, contrary to increased L2 cache improving performance.

If Intel 3 was that much less expensive than Intel 7, it would have made sense to release a mobile version of Raptor Lake on Intel 3 instead of the mess that Meteor Lake is. It's not like they didn't already mostly port the Raptor Cove and Crestmont cores over to that IP already.

Okay, but they needed Meteorlake to sort out the difficulties of splitting into tiles. Sticking with monolithic for another generation delays disaggregation succeeding for another generation. Meteorlake actually didn't turn out all that bad and was an improvement over Raptorlake in mobile. The learnings likely resulted in Lunarlake.

Also their goal was to move to 18A quickly as possible, so having more on Intel 3 would mean more spent on a process with a shorter lifespan over say focusing on the ultimate goal which was 18A. This is on top of cutting out designs to save money because the company was struggling financially.

 

[OneEng2]

Considering Intel has said in the past that Intel 7 is quite more expensive for them than Intel 4/3, I don't see 18A costing an arm and leg. Specially given High-NA was postponed to 14A.

The fact Intel will replace their Intel 7 Raptor Lake mainstream designs with 18A based Wildcat Lake is an indication for me that 18A process costs should be very healthy for their margins.

GAA with BSPDN has many more process steps than any current FinFET process (inside or outside of Intel). 18A development costs are around 20Bn to date. I fail to see how it is possible that 18A will not be a substantially more expensive node than Intel 4/3.

Can you elaborate on how you believe 18A is cost effective (comparatively speaking)?

 

[DavidC1]

The recent news that Intel was delaying CWF is also not that promising.

CWF delays are packaging, not process, which is why Pantherlake is coming first, when originally it was CWF before Panther.

BSPDN should also be providing a good deal more effective transistor density. IIRC, an additional 30% simply by allowing more compressed layout options with fewer vias to interrupt logic density.

There's pretty much no optical shrink anymore. So 30% density increase(not 30% size decrease, which is 40% density increase) is entirely due to PowerVia and nothing else. Welcome to semi scaling 2025.

So what took an easy optical shrink now requires immense, and once in a decade changes to get fraction of the benefits. We used to get Gold with a pickaxe, now we're getting Tin with an Excavator.

Strange. Intel always had the highest transistor density processes, and lowest latency cache ....... once upon a time.

Intel never had the highest density process, they just happened to release next gen before others. They always had the highest performing process.

The much touted copper interconnect 0.18u AMD Dresden process was substantially behind Intel's ALU 0.18u process - the latter had nearly 30% higher Idsat. And Intel's process came earlier too.

The "2-3 year advantage" was something like this:
-Generation+ advantage in performance: 2-2.5 years
-1 year TTM compared to competitors
-0.5 gen behind density: -1 year.

The 22nm Intel process was according to their own numbers only 30% smaller than 28nm TSMC, when logic would dictate it should have been 50% smaller. So in density Intel 22nm was like ~25nm TSMC. So 20nm TSMC was ahead of Intel 22nm in density significantly, but was way behind in introduction and 22nm probably wasn't beat in performance until plus variants of N16.

 

[lightisgood]

If Intel 3 was that much less expensive than Intel 7, it would have made sense to release a mobile version of Raptor Lake on Intel 3 instead of the mess that Meteor Lake is. It's not like they didn't already mostly port the Raptor Cove and Crestmont cores over to that IP already.

I3 capacity is not so high, but GNR-SP/AP have very much die-area.

 

[DavidC1]

Can you elaborate on how you believe 18A is cost effective (comparatively speaking)?

I don't think 18A is cheaper than Intel 3 but Intel 7 really pushed using multi-patterning while 18A uses more EUV steps than Intel 3 and cancels out some of the cost increases due to PowerVia.

18A is basically Intel 3 with PowerVia and RibbonFET. I'm expecting almost no optical shrinks.

 

[lightisgood]

Intel never had the highest density process, they just happened to release next gen before others. They always had the highest performing process.

Yes.
Intel is the king of HPC.
I'm looking forward to seeing that i18A demonstrate it.

Intel's Celestial dGPUs Are Expected To Feature The Xe3P Architecture, Will Likely Use Intel Foundry Instead of TSMC

Intel's next-gen Celestial discrete GPUs are expected to feature the Xe3P architecture and could potentially be developed by the IFS.

wccftech.com

If Xe3P really uses i18A, I think that IFS could take NVIDIA as new customer.

 

[Hitman928]

I don't think 18A is cheaper than Intel 3 but Intel 7 really pushed using multi-patterning while 18A uses more EUV steps than Intel 3 and cancels out some of the cost increases due to PowerVia.

18A is basically Intel 3 with PowerVia and RibbonFET. I'm expecting almost no optical shrinks.

Power Via increases costs.

 

[lightisgood]

Power Via increases costs.

i18A is able to choose leaving out PowerVia.

 

[511]

Is LNC too "wide" of a core for N3 though? Zen 5 is built on a N5 class node, with better perf/watt than LNC across the curve. I think they could get another tock out of 18A without shifting the perf/watt curve too much to the upper right and have a regression at lower power (cough RKL cough). If they fix their physical design too.

It matched Zen5 in David Huang testing with LNC in LNL vs Zen5 in strix Point with the horrible uncore of MTL/ARL the core suffered quite a lot .