Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

Page 433 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

Tigerick

Senior member
Apr 1, 2022
851
802
106
Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

Intel Alder Lake - NIntel Wildcat LakeIntel Lunar LakeMediatek D9500
Launch DateQ1-2023Q2-2026 ?Q3-2024Q3-2025
ModelIntel N300?Core Ultra 7 268VDimensity 9500 5G
Dies2221
NodeIntel 7 + ?Intel 18-A + TSMC N6TSMC N3B + N6TSMC N3P
CPU8 E-cores2 P-core + 4 LP E-cores4 P-core + 4 LP E-coresC1 1+3+4
Threads8688
Max Clock3.8 GHz?5 GHz
L3 Cache6 MB?12 MB
TDP7 WFanless ?17 WFanless
Memory64-bit LPDDR5-480064-bit LPDDR5-6800 ?128-bit LPDDR5X-853364-bit LPDDR5X-10667
Size16 GB?32 GB24 GB ?
Bandwidth~ 55 GB/s136 GB/s85.6 GB/s
GPUUHD GraphicsArc 140VG1 Ultra
EU / Xe32 EU2 Xe8 Xe12
Max Clock1.25 GHz2 GHz
NPUNA18 TOPS48 TOPS100 TOPS ?






PPT1.jpg
PPT2.jpg
PPT3.jpg



As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



LNL-MX.png
 

Attachments

  • PantherLake.png
    PantherLake.png
    283.5 KB · Views: 24,029
  • LNL.png
    LNL.png
    881.8 KB · Views: 25,523
  • INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg
    INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg
    181.4 KB · Views: 72,431
  • Clockspeed.png
    Clockspeed.png
    611.8 KB · Views: 72,319
Last edited:

TESKATLIPOKA

Platinum Member
May 1, 2020
2,696
3,260
136
Arrow lake performance will be very big.. intel has veen good at hiding its true performance
They are masters of hiding the performance. The hid It so good, that they themselves can't find It any longer. :p

Performance wise ST nothing much in my opinion, nT could surprise or not, who knows.
If they can reign in the power consumption, It will be good enough.
 

TESKATLIPOKA

Platinum Member
May 1, 2020
2,696
3,260
136
Desktop vs Laptop CPUs aren't the same though. The few % differences in internal firmware, memory latency, binning, idle power differences will all add up, plus motherboard settings which might increase peak power significantly for few % faster performance.
I know, but there was no better comparison available.
 

TESKATLIPOKA

Platinum Member
May 1, 2020
2,696
3,260
136
they have to, its on N3B
Not necessarily, If they once more go for max performance, then It doesn't matter If the process is better than what they used with RPL.
Power consumption would be atrocious, just the performance or perf/W will be higher.
Mobile version could be interesting with more limited TDP, although I am not that happy with the old MTL SoC tile.

Then what I see as the biggest problem for Intel is that they plan ARL for both mobile and desktop. At least RPL was made by them. ARL will have only the interposer made by themselves. In 2023 the foundry business made a $7 billion operating loss, then this year and the next It could be only worse.
 
Last edited:

511

Diamond Member
Jul 12, 2024
4,566
4,190
106
Not necessarily, If they once more go for max performance, then It doesn't matter If the process is better than what they used with RPL.
Power consumption would be atrocious, just the performance or perf/W will be higher.
Mobile version could be interesting with more limited TDP, although I am not that happy with the old MTL SoC tile.
Me neither the Uncore is horrendous Intel 4 CPU themselves are efficient though
 

Wolverine2349

Senior member
Oct 9, 2022
525
179
86
Rumour has it that bartlett lake is not for regular consumers but for some special vertical like networking or something. So, it may be available only thru some specific oem channels for specific customers. Just guessing.

Also, if it isn’t for the general public, then it may not clock as high as they would want to keep the power usage and heat under control in an industrial setting. Again, just guessing.
Well could buy it 2nd hand from an OEM if they have a 12 p core die on a ring bus.
 

jpiniero

Lifer
Oct 1, 2010
16,815
7,257
136
Rumour has it that bartlett lake is not for regular consumers but for some special vertical like networking or something. So, it may be available only thru some specific oem channels for specific customers. Just guessing.

Appears it might be extended to consumers because AI.
 

IEC

Elite Member
Super Moderator
Jun 10, 2004
14,600
6,084
136
12 P-cores necessitates a longer ring bus (if that is what they are using). Which would have a latency impact and make it likely worse for gaming than an 8 P-core part.
 

511

Diamond Member
Jul 12, 2024
4,566
4,190
106
12 P-cores necessitates a longer ring bus (if that is what they are using). Which would have a latency impact and make it likely worse for gaming than an 8 P-core part.
Not really it will be shorter than 13900K die assuming nothing is added cause 4E cores are roughly 1.2-1.3 times P cores so for 4P cores you roughly save an area worth of an additional P cores
 

Attachments

  • 11715907-4521-4c3d-8e75-3ec5d8f82746_1024x602.png
    11715907-4521-4c3d-8e75-3ec5d8f82746_1024x602.png
    86 KB · Views: 21
  • 6088a70e-2300-4741-ae91-37abb0ee2d8d_1022x185.png
    6088a70e-2300-4741-ae91-37abb0ee2d8d_1022x185.png
    26 KB · Views: 21

jdubs03

Golden Member
Oct 1, 2013
1,282
902
136
Looks like we got the full lineup:
 

Wolverine2349

Senior member
Oct 9, 2022
525
179
86
I have heard Intel 10nm process node is expensive? Is that true or no?

I mean if it is indeed more expensive than TSMC or their 20A node, wouldn't Intel be better off making the 12 P core only model based on Arrow Lake instead of Raptor Cove?

Or is it not true that 20A and TSMC node they are putting Arrow Lake on is less expensive than their 10nm process node?

Or is Intel simply trying to capture the LGA 1700 market and knock out AMD AM4 market segment regardless and they have lots more 10nm capacity so better off to do 12 + 0 on that rather than 20A or TSMC?
 

DavidC1

Golden Member
Dec 29, 2023
1,854
2,986
96
I have heard Intel 10nm process node is expensive? Is that true or no?

I mean if it is indeed more expensive than TSMC or their 20A node, wouldn't Intel be better off making the 12 P core only model based on Arrow Lake instead of Raptor Cove?
It would be because it's using DUV but it's a very mature process so switching to a brand new one like 20A or even N3 wouldn't necessarily be cheaper initially. When they mature sure.
Not really it will be shorter than 13900K die assuming nothing is added cause 4E cores are roughly 1.2-1.3 times P cores so for 4P cores you roughly save an area worth of an additional P cores
It doesn't work like this. The cores are a rectangle. And the whole die needs to be a rectangle. It'll just end up being a slightly smaller die instead. Look at the Raptorlake die.
 

511

Diamond Member
Jul 12, 2024
4,566
4,190
106
I have heard Intel 10nm process node is expensive? Is that true or no?
Yes it is using SAQP basically to print a pattern they have to go through the process 4 times EUV would have made that 1 times so simplification also 10nm has weird quirk like Cobalt being the
I mean if it is indeed more expensive than TSMC or their 20A node, wouldn't Intel be better off making the 12 P core only model based on Arrow Lake instead of Raptor Cove?

Or is it not true that 20A and TSMC node they are putting Arrow Lake on is less expensive than their 10nm process node?
First 20A is a half node like Intel 4 it only contains enough library to make a CPU and minimum IO just like Intel 4 you can't make a Monolithic SOC hencs the derisking of Process basically Intel 4 and 3 are one full node and Intel 20A and 18A are one the later being superset of previous half node also the cost 20A is expensive than Intel 7 but for the PPA it becomes better their foundry cost structure improves why do you think they are raking losses in Foundry it's the hidden truth you need good cost structure if you wanna run foundry they were hiding inefficiency in their foundry for years at least since Brian Kranzich
 

511

Diamond Member
Jul 12, 2024
4,566
4,190
106
It's cheap... but presumably what they mean by expensive is that the yields are still garbage.
The yields are not garbage tbh otherwise we will not see such big dies of EMR even 13900K is a large die i would consider anything above 200mm2 to be large die
 
  • Like
Reactions: DavidC1

511

Diamond Member
Jul 12, 2024
4,566
4,190
106
It would be because it's using DUV but it's a very mature process so switching to a brand new one like 20A or even N3 wouldn't necessarily be cheaper initially. When they mature sure.

It doesn't work like this. The cores are a rectangle. And the whole die needs to be a rectangle. It'll just end up being a slightly smaller die instead. Look at the Raptorlake die.
Yeah i meant that the die will be smaller cause you saved some area sorry if i sounded confusing 😅
 

CakeMonster

Golden Member
Nov 22, 2012
1,630
809
136
After the thread priority and core parking drama with AMD, I hope to see some in-depth analysis of the behavior of Arrow Lake when it arrives. Hopefully compared to Z5 somewhat improved/tweaked.