Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[coercitiv]

I'm holding out hope that Arrow Lake is competitive (and fixes Intel 13th/14th gen stability issues) so I have an excuse to build or upgrade another system in the next six months.

On the other hand, the realist in me expects marginal gains overall with some regressions. There are just too many known items working against ARL:
1) Clock speed regression (even vs most optimistic "leaks")
2) Tile architecture = there will be some performance regressions due to this (latency and power penalties vs monolithic)
3) Lack of SMT
4) New platform/motherboards - I expect some things to be broken at launch judging from recent Intel and non-Intel launches

Not too much longer til we know for sure.

ARL can bring a decent upgrade to your 12600K system, assuming you go for the Ultra 5 or Ultra 7:

1. 6-12% higher clocks + 10%+ higher IPC, so think 15-20%+ higher ST performance
2. Regression from tiled arch. already included in the rough & pessimistic estimate above
3. SMT removal will be non-issue if you don't do rendering or some other similar thread bound work, and in the case of Ultra 7 you'll get 12 E cores, the E cores alone will have comparable MT perf with your 12600K
4. The new platform jinx is a given, this year has managed to plague everything (from hardware launches to Microsoft software), but we all know it when buying early.

What is a better estimate?

He's arguing the 14% uplift was given for RWC in MTL mobile, which saw a regression against RPL mobile. See my previous post here. Unfortunately applying this regression to ARL only gives us a lower bound for the possible uplift, as ARL is likely to compensate for some of it. (more L2, maybe faster tile interconnect etc.)

 

[inf64]

compare vs MTL then to RPL

Well as per David Huang:

 

[cebri1]

Well as per David Huang:

View attachment 105519

Was there really a regression? I remember Intel launched 2 BIOS updates that improved performance significantly at ISO frequencies. Is intel comparing against launch RWC or current RWC?

 

[desrever]

Well as per David Huang:

View attachment 105519

13700H is almost 10% more IPC than 155H, (this isn't even RPL refresh, which has like a 1% improvement from RPL). Using the 14% intel figure would make ARL 4.5% more IPC than RPL.

1.045*5.7/6 = 0% ST improvement average?

 

[SiliconFly]

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[9949asd]

13700H is almost 10% more IPC than 155H, (this isn't even RPL refresh, which has like a 1% improvement from RPL). Using the 14% intel figure would make ARL 4.5% more IPC than RPL.

1.045*5.7/6 = 0% ST improvement average?

the 14% is base on intel ppt LNL vs MTL, the ARL p core ipc will higher than LNL’s p core for sure.

 

[inf64]

the 14% is base on intel ppt LNL vs MTL, the ARL p core ipc will higher than LNL’s p core for sure.

How do you know that any how much higher? It's all just guesswork until someone tests ARL-S (which kinda already happened with Jaykihn guy).

 

[SiliconFly]

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[SiliconFly]

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[gdansk]

If you're talking about discerning between 5% or 10% differences then for many benchmarks that'll be within margin-of-cooling.

So I'm guessing people won't agree even after the chips are available.

 

[desrever]

Wrong. MTL has clock regression of around 4% to 5% over previous gen equivalent sku that you haven't taken into account. Once included, the *overall* performance regression of MTL is only around 4% to 5% over previous gen equivalent sku, which includes both tile penalty *and* IPC regression combined.

I don't have the exact numbers (maybe other can help shed some light), but the MTL tile penalty itself is estimated to be around 3% by people in this forum which I too believe is probably close. So, the overall IPC regression (if any) for the RWC core is pretty much negligible.

You're estimate is light-years off from the actual.

It literally says performance/GHz in the chart which is IPC.

 

[SiliconFly]

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[dullard]

Even if IPC is above 14%, once we factor in clock regression & tile penalty, the overall ST performance will still take some hit. I'm guessing the final will be around 9% to 10% ST perf uplift minimum. But some others say only 5%. Only time will tell.

I do have to get quite a laugh about all this. Compare Raptor Lake IPC to Meteor Lake IPC. Then compare Meteor Lake IPC to Lunar Lake IPC. Then assume Arrow Lake IPC is similar to Lunar Lake IPC (cache and node differences probably aren't major contributors). Then assume frequencies (which are reasonably known). Then waive hands about how long the turbo speed can be maintained. Do all the math. And finally come up with 5% to 9%/10%.

Or skip all that hand waiving and calculations and just go with the age-old Intel leak of 3% to 8% until we have chips in a couple months. https://forums.anandtech.com/attachments/img_0842-jpeg.105351/

Both of which are pretty much in line with the Arrow Lake leak that we already have had: https://videocardz.com/newz/intel-c...s-cpu-spotted-in-geekbench-with-5-5-ghz-boost

 

[SiliconFly]

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[Abwx]

True & very true. But even if we consider a meager 5% increase for ARL-S top sku over 14900K in GB6 ST, it's still a few percentage points ahead of competition top sku 9950X.

A few negative percentage points eventualy, because the 9950X is 6% ahead of the 14900K in GB 6.3 ST, and before you ask Computerbase s 14900K score 3236 pts, wich is above GB submissions average.

AMD Ryzen 9 9900X und 9950X im Test: Benchmarks in neuen Anwendungstests

Ryzen 9 9950X & 9900X im Test: Benchmarks in neuen Anwendungstests / Intel-Instabilität und AGESA-Updates sind die (neue) Tagesordnung

www.computerbase.de

 

[jdubs03]

ARL-S ST in GB6, in all likelihood will average about the same as the 9950X. Realistically anywhere from a few percentage points behind to a few ahead.

 

[SiliconFly]

.

 

[OriAr]

Considering both RPL and MTL have only 2P+4E It's not really surprising that nT will be better.
BTW, what do you consider as a huge upgrade? +30% or more in nT?

Here is a table where I compare mobile MTL vs ARL. Not accurate, just an example of how much better It could be.
MTL P-core: 100 points
MTL P-core HT: 25 points
MTL E-core: 65 points
ARL P-core: 110 points
ARL E-core: 90 points

Thread count	Ultra 3 105UL 2P+4E	ARL 4P+4E	Difference in %
1	100	110	+10%
2	200	220	+10%
3	265	330	+24.5%
4	330	440	+33.3%
5	395	530	+34.2%
6	460	620	+34.7%
7	485	710	+46.4%
8	510	800	+56.9%

I was comparing it to 4+0 i3 which means on paper it should be roughly 70% better in MT perf.
Of course the real world is different but I'd be stunned if it's not at least +50% increase.

 

[DavidC1]

I could go on and on with links. In the average software, AMD's SMT gained more than Intel's HT. As the years go on, SMT's improvement is getting less and less on average.

The reduction in HT's gain over the years can be explained(at least partially for now) by the fact there's diminishing returns to extra threads, which were very useful in the quad core days, but less on 8 cores, and definitely not nowadays with 16 or even 24 cores on them.

I know back in the days when they were saying HT was useless for games, but that was on the quad core chips. On the dual core ones, it was responsible for 20-30% gain in frame rates!

As for Intel's lack of SMT gains compared to AMD it can be explained by their architectural choices. I speculate one of the reason is due to AMD using distributed schedulers versus shared ones on Intel. HT further exacerbates the negative effect of sharing.

The way HT resources are allocated affects it too. I don't remember off the top of my head but they aren't identical. You can also optimize HT resource allocation to optimize more for ST vs MT.

Well as per David Huang:

View attachment 105519

Geekerwan's test showed the Desktop variant is faster than the mobile, the gap enough to explain the differences between Meteorlake(mobile only) and Raptorlake. And I know that this difference always existed.

You want to use 50% chance of being correct as a concrete evidence, go ahead. Mobile testing has serious issues for this very reason. Even on the firmware level Intel talks about power vs performance optimization and this was back in the Conroe days!

 

[TESKATLIPOKA]

I was comparing it to 4+0 i3 which means on paper it should be roughly 70% better in MT perf.
Of course the real world is different but I'd be stunned if it's not at least +50% increase.

So you meant a desktop comparison.
I don't think RPL 4P is weaker in nT than RPL 2P+4E, maybe a bit and It depends on actual clocks. Couldn't really find a meaningful comparison.

 

[511]

So you meant a desktop comparison.
I don't think RPL 4P is weaker in nT than RPL 2P+4E, maybe a bit and It depends on actual clocks. Couldn't really find a meaningful comparison.

Tbh RPL 4P is more likely going to be 2P+8E equivalent

 

[SteinFG]

Just noticed TPU making up process node names 😄 It's gonna be funny to see, as cpu generations pass, are they gonna continue making up node names that don't exist? The correct node for 6000E is Intel 3.

 

[TESKATLIPOKA]

Tbh RPL 4P is more likely going to be 2P+8E equivalent

Certainly not in nT.
13100F(4P+0E, 58W TDP -> 75W in Prime95) managed only 8844 points in CB R23.
i7-1365U(2P+8E, 28W sustained) 9576 points in CB R23.
So higher score at 1/2 TDP or less.
These E-cores despite their disadvantages are not just for show.

 

[Wolverine2349]

Why are the Skymont e-cores in clusters of 4 rather than individual like the P cores on the ring?

I mean if the Skymont really have IPC of Raptor Cove, why not make them individual or sell such a CPU and it could be the all P core Raptor Lake substitute for a homogenous arch but maybe lower clocks but still 12700K P core HT disabled capable as 12700K runs 4.7GHz all core.

 

[Hitman928]

Why are the Skymont e-cores in clusters of 4 rather than individual like the P cores on the ring?

I mean if the Skymont really have IPC of Raptor Cove, why not make them individual or sell such a CPU and it could be the all P core Raptor Lake substitute for a homogenous arch but maybe lower clocks but still 12700K P core HT disabled capable as 12700K runs 4.7GHz all core.

They’d have to go to a mesh interconnect which has significant power and latency consequences.