Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[igor_kavinski]

how much slower will NVL be than ARL .

If they actually manage that (NVL slower than even ARL), LBT should just resign now (he has the tape-out results). I hope he sells his shares as soon as he sniffs something burning and gets the hell out of there.

 

[511]

If they actually manage that (NVL slower than even ARL), LBT should just resign now (he has the tape-out results). I hope he sells his shares as soon as he sniffs something burning and gets the hell out of there.

Bruh NVL preliminary data has already leaked also NVL is pat product so you can blame it on him that should be easy peasy for you 🤣

 

[igor_kavinski]

Bruh NVL preliminary data has already leaked also NVL is pat product so you can blame it on him that should be easy peasy for you 🤣

I'm tired of blaming him. I'm suffering from a chronic case of "Blame Pat" syndrome. I want this to be over. LBT, sell the fabs or fire half the company. Do it. NOW!

 

[511]

I'm tired of blaming him. I'm suffering from a chronic case of "Blame Pat" syndrome. I want this to be over. LBT, sell the fabs or fire half the company. Do it. NOW!

NVL is good not half baked like ARL tbh. It will make Desktop great again.

 

[igor_kavinski]

NVL is good not half baked like ARL tbh. It will make Desktop great again.

Imma gonna skip it no matter what. Currently I don't see any reason why I would want it.

 

[511]

Imma gonna skip it no matter what. Currently I don't see any reason why I would want it.

Makes sense you took a arrow to the Knee 🤣

 

[coercitiv]

Imma gonna skip it no matter what. Currently I don't see any reason why I would want it.

Even after this reply I would gauge the probability of you buying NVL-S at 50%, going up to 80% if Intel delivers a proper big cache.

 

[LightningZ71]

I'm tired of blaming him. I'm suffering from a chronic case of "Blame Pat" syndrome. I want this to be over. LBT, sell the fabs or fire half the company. Do it. NOW!

Personally, I blame Noyce and Moore. Intel wouldn't exist without them, and by not existing, they wouldn't have made the mistakes that they have made...

 

[igor_kavinski]

Even after this reply I would gauge the probability of you buying NVL-S at 50%, going up to 80% if Intel delivers a proper big cache.

Nah. I'm done. Seeing current limits of silicon and the slow (lazy?) state of incremental improvements, I will skip NVL and maybe upgrade to Zen 6 when it crashes in price due to Zen 7 ample availability.

I'm actually more interested in seeing some cooling innovation that gives plebs the same cooling capacity as custom cooled rigs.

 

[AcrosTinus]

Nah. I'm done. Seeing current limits of silicon and the slow (lazy?) state of incremental improvements, I will skip NVL and maybe upgrade to Zen 6 when it crashes in price due to Zen 7 ample availability.

I'm actually more interested in seeing some cooling innovation that gives plebs the same cooling capacity as custom cooled rigs.

*was too negative*
I am also on the hold once the Ultra 7 is stabilized, will take a look once 2nd Gen DDR6 systems are out.

 

[poke01]

Nah. I'm done. Seeing current limits of silicon and the slow (lazy?) state of incremental improvements, I will skip NVL and maybe upgrade to Zen 6 when it crashes in price due to Zen 7 ample availability.

I'm actually more interested in seeing some cooling innovation that gives plebs the same cooling capacity as custom cooled rigs.

Most of the CPU innovation will come from RISC-V and ARM and co.

As for DIY you will be stuck with AMD for a long while

 

[reb0rn]

I have no idea, so many here should just be hired by intel so easy to solve all as I see.......

 

[poke01]

I have no idea, so many here should just be hired by intel so easy to solve all as I see.......

Not me but others could here are definitely capable and could do a better job than Intels 4 prior CEOs

 

[adroc_thurston]

and could do a better job than Intels 4 prior CEOs

Oh hell no, Intel is a labyrinthine structure.
A curse for anyone and everyone heralding it.

 

[igor_kavinski]

Oh hell no, Intel is a labyrinthine structure.
A curse for anyone and everyone heralding it.

Yeah, only I can succeed because I don't mind getting to the bottom of things, especially when I'm passionate about it. If there are things I don't understand (like process related limits), I'll just use TSMC as an excuse (they did it, are you admitting that you guys are inferior than TSMC?). But yeah, for me to succeed and remembered as the best CEO Intel ever had, they need to give me complete control, right down to firing someone on the spot if I think they are being a detriment to my goal.

 

[igor_kavinski]

*was too negative*
I am also on the hold once the Ultra 7 is stabilized, will take a look once 2nd Gen DDR6 systems are out.

What workloads does your 265K usually crash in? I haven't faced a serious crash on my 245KF yet during normal use but then I haven't used it for 24 hours straight yet. In your case, it seems like possibly a bad sample (could be one reason why they are having a firesale on 265K) or the mobo needs the latest BIOS and try running with only Intel base profile or 200S Boost profile and see if the crashes persist. If they still do, either bad mobo, some other finicky hardware causing the crashes (process of elimination to identify) or finally bad CPU sample.

 

[OneEng2]

NVL is good not half baked like ARL tbh. It will make Desktop great again.

I suspect that NVL will be to ARL as Zen 3 was to Zen 2. In other words, I am thinking it is going to be a pretty good product.

Even after this reply I would gauge the probability of you buying NVL-S at 50%, going up to 80% if Intel delivers a proper big cache.

I do wonder about the big cache implementation. In AMD's X3D it is great for workloads that thrive on low latency memory access (like games).

I suspect even a poor implementation of Intel big cache would greatly improve the overall memory access latency. Maybe not as well as AMD's X3D implementation, but it might not matter overall.

 

[511]

I suspect even a poor implementation of Intel big cache would greatly improve the overall memory access latency. Maybe not as well as AMD's X3D implementation, but it might not matter overall.

Intel's version the cache is on the same die as the cores no HB a normal compute tile with extra cache

 

[Geddagod]

Intel's version the cache is on the same die as the cores no HB a normal compute tile with extra cache

Hence it likely being a worse implementation, from the perf side.
According to AMD you can't achieve the very low 4 cycles latency hit that adding all that extra capacity without 3D stacking it.

 

[coercitiv]

I suspect even a poor implementation of Intel big cache would greatly improve the overall memory access latency. Maybe not as well as AMD's X3D implementation, but it might not matter overall.

It does not have to be as fast, it's still a big chunk of cache that is significantly faster the RAM pool. I'm just cautious because it's Intel, they seem to introduce unexpected flaws in many of their recent products.

Intel's version the cache is on the same die as the cores no HB a normal compute tile with extra cache

Are we sure about this? They'll have two 8+16 compute die designs?

 

[511]

Hence it likely being a worse implementation, from the perf side.
According to AMD you can't achieve the very low 4 cycles latency hit that adding all that extra capacity without 3D stacking it.

Bruh what? There ain't no way HB is superior to monolithic in performance unless you are talking about very large big dies where you can't fab it. Please get your facts checked.

Are we sure about this? They'll have two 8+16 compute die designs?

Yes the bLLC and the normal cache version

 

[Geddagod]

Bruh what? There ain't no way HB is superior to monolithic in performance unless you are talking about very large big dies where you can't fab it. Please get your facts checked.

 

[coercitiv]

There ain't no way HB is superior to monolithic in performance unless you are talking about very large big dies where you can't fab it.

Monolithic can end up paying a bigger latency cost due to higher signaling distance. Vertical stacking keeps max distance under control. My understanding is that, as far as latency is concerned, there's an area threshold where stacking pulls ahead in terms of performance.

 

[511]

Monolithic can end up paying a bigger latency cost due to higher signaling distance. Vertical stacking keeps max distance under control. My understanding is that, as far as latency is concerned, there's an area threshold where stacking pulls ahead in terms of performance.

But it is dependent on the distance as well and how their L3 is architected for this it all comes down to how they are doing it

 

[dr1337]

Why isn't it a problem for Apple and their LLCs?

Idk how much AMD marketing is really applicable to reality/Intel, none of these companies really want to give all the details. Its easy to say signaling distance without giving any numbers.