Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[511]

If I am less pessimistic, I would call the reintroduction of SMT a positive thing, but somehow my gut tells me, this will be at the cost of ST performance gains because time has to be invested into resurrection and hardening to prevent a SpectreV-X. Time that could have gone into the 1T performance. A super wide P-Core or the so called rumored RU is officially a bed time story.

It's majorly in DC though

 

[OneEng2]

For some reason, AMD gets a much bigger boost from SMT than Intel .... which is ironic since Intel introduced it to x86 far before AMD got it.

SMT4 for Intel anyone?

 

[Doug S]

For some reason, AMD gets a much bigger boost from SMT than Intel .... which is ironic since Intel introduced it to x86 far before AMD got it.

SMT4 for Intel anyone?

I was honestly going to suggest the same thing. If you're going to do it, go all the way with it and support SMT4 or even SMT8 like IBM. The additional cost to "go bigger" is less than the cost to do it at all.

I hate on Intel's product segmentation all the time, but it wouldn't make me sad at all if only Xeon and Core i9 type stuff supported SMT, and it was disabled on everything else.

 

[igor_kavinski]

I hate on Intel's product segmentation all the time, but it wouldn't make me sad at all if only Xeon and Core i9 type stuff supported SMT, and it was disabled on everything else.

Just learned few days ago from someone that out of three samples of Alder Lake CPUs with functioning AVX-512 (with mobos that have patched BIOS and microcode), none had issue-free AVX-512 execution. Some cores always error out on some instructions while others work fine. So my speculation is that (like everything else), Intel LIED about hybrid cores as the reason why AVX-512 was disabled in their consumer CPUs. They probably found or were notified of errors too close to launch and then a decision was made to axe AVX-512. Pat was the CEO. Makes me wonder how many other lies he was responsible for.

 

[jpiniero]

Some cores always error out on some instructions while others work fine.

That's kind of what you would expect to happen if an thread just magically moved from a P Core to an E core and tried to do an AVX-512 instruction.

 

[gdansk]

SMT4 for Intel anyone?

It was a punchline but as an ISA's typical workload becomes more and more enterprise-y it seems they trend toward more SMT, not less.

 

[igor_kavinski]

That's kind of what you would expect to happen if an thread just magically moved from a P Core to an E core and tried to do an AVX-512 instruction.

Nope. Even patched BIOS/microcode do not allow enabling AVX-512 with E-cores. The E-cores need to be explicitly disabled for the AVX-512 option to appear in BIOS settings. So the errors are happening with only P-cores enabled. May not matter for something like a PS3 emulator but for anyone actually doing serious work, the errors would've been frustrating. Rather than risk admitting that they messed up, Pat decided to let Intel cover it up.

 

[jpiniero]

Nope. Even patched BIOS/microcode do not allow enabling AVX-512 with E-cores. The E-cores need to be explicitly disabled for the AVX-512 option to appear in BIOS settings. So the errors are happening with only P-cores enabled.

That was the original intention, yes. It's possible that a patch would mess things up, esp if it didn't do things like do the proper voltage adjustments to handle AVX-512.

 

[OneEng2]

It was a punchline but as an ISA's typical workload becomes more and more enterprise-y it seems they trend toward more SMT, not less.

As stated, the only one I can remember doing this was IBM IIRC. I am thinking that you don't get near the boost from SMT4 as you get from nothing to SMT2. ... and you really have to add some serious execution units across the board to do it.

I just wonder if it isn't a better PPA to just add another entire SMT core?

 

[511]

i

https://twitter.com/x/status/1950177712804426225

 

[511]

MLID made PTL ramblings anyone have any idea what he was rambling about?

 

[Tarkin77]

MLID made PTL ramblings anyone have any idea what he was rambling about?

IPC increase <10%

 

[511]

IPC increase <10%

Well since it's a Lion Cove refresh even 5% would be good but he will say they failed

 

[AcrosTinus]

Well since it's a Lion Cove refresh even 5% would be good but he will say they failed

Rando with a microphone sets a bar for a multinational company, if his imaginary bar is not reached, that company failed and is never going to recover. Delusions of grandeur !

 

[511]

Rando with a microphone sets a bar for a multinational company, if his imaginary bar is not reached, that company failed and is never going to recover. Delusions of grandeur !

Not to mention people buying this

 

[Magio]

Well since it's a Lion Cove refresh even 5% would be good but he will say they failed

That's the MLID way, set high expectations for minor refreshes and then slam the refresh for not meeting them.

Tho of course in this case, Intel's P core is and has been a disappointment (in PPA, PPW, ...) for some years now. Just no one paying attention should expect Cougar Cove to fix that.

Hopefully 18A is a meaningfully better node than N3B and there'll still be improvements to performance that way.

 

[Josh128]

View attachment 127924i

https://twitter.com/x/status/1950177712804426225

What an absolute cluster f of product offerings. No wonder Intel are failing, they seem to have no clear direction, rhyme, or reason to their designs and production lithography choices. Its all over the place.

 

[igor_kavinski]

What an absolute cluster f of product offerings. No wonder Intel are failing, they seem to have no clear direction, rhyme, or reason to their designs and production lithography choices. Its all over the place.

And they are too proud to ask us for advice. Morons.

 

[511]

What an absolute cluster f of product offerings. No wonder Intel are failing, they seem to have no clear direction, rhyme, or reason to their designs and production lithography choices. Its all over the place.

It's not cluster F if you think how they have planned this all of this done with like 5-6 Tiles 3 are common btw.

 

[igor_kavinski]

It's not cluster F if you think how they have planned this all of this done with like 5-6 Tiles 3 are common btw.

They are so good at planning for failure. It's an art form.

 

[reb0rn]

How many of you got sacked from intel and just rage bait here

 

[511]

How many of you got sacked from intel and just rage bait here

ask igor

 

[igor_kavinski]

ask igor

I'm baiting them to hire me

I'll escape with the Tejas prototype if it's the last thing I do!

 

[poke01]

I see no problem with Intels client roadmap, to be honest it’s better than AMDs especially
for laptop.

Server is a sour pudding though, that’s beyond fixing this decade

 

[poke01]

I see Panther lake being even better than ARL-h for battery related tasks. Can’t wait, not every thing is about IPC.

The fact that PTL doesn’t use Arrow lakes awful uncore and is similar to lunar lake is a massive plus.