uzzi38
Platinum Member
- Oct 16, 2019
- 2,746
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Yes, but MTL-S launches ahead of ARL-S by a good margin from the looks of it. Even if both are part of the same SKU stack and branded as the same gen.
The silicon might be ready sooner, but I expect they'll delay the actual launch to coincide with ARL. OEMs will not be willing to adopt a platform they can't upsell beyond the i5 tier. Nor will MTL-S offer any other meaningful advantages for mass market OEM desktops. And it'll be a joke in DIY.
DrMrLordX
Lifer
- Apr 27, 2000
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For server work, power per socket is also important. Perf/watt is the ultimate indicator of whether a CPU can be successful in the enterprise space, and Zen4/Genoa is already so dense that many enterprise customers don't specifically need more cores/socket. A massive increase in perf/watt for Zen5 and/or a massive IPC increase would be more than enough for customers to pick it over Genoa or whatever Intel offers in competition. Plus now AMD has Bergamo (and successors) coming for people that need even higher core counts per socket.
Zen5 is supposed to be a bigger deal than Zen4 (relative to its predecessors). Should be interesting to see how that works out. AMD already demonstrated that they can make big jumps (zen2->zen3) without changing node, so staying in the same node family (n5->n4p) shouldn't be a great hindrance to them. Meanwhile, we're to expect that Granite Rapids is going to be some holy grail, when it's already been "reimagined" at least once and is far behind its original launch window. People should be skeptical to say the very least.
IntelUser2000
Elite Member
- Oct 14, 2003
- 8,686
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According to HX, Emerald Rapids is 64 core but 1-2S only. So that means that 4-8S Granite Rapids can come early 2024, but 1-2S Granite Rapids quite a bit later, maybe even late 2024.
They seem to be putting an emphasis on Enterprise customers. Maybe this is also volume-related? Enterprise started with Pentium Pro, and then Xeon MP for Intel. Relatively low volume, but customers tend towards the high end.
Which would greatly improve pricing flexibility and ability to actually sell high end chips rather than current semi-fake pricing today.
They seem to be putting an emphasis on Enterprise customers. Maybe this is also volume-related? Enterprise started with Pentium Pro, and then Xeon MP for Intel. Relatively low volume, but customers tend towards the high end.
Which would greatly improve pricing flexibility and ability to actually sell high end chips rather than current semi-fake pricing today.
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I patiently await Zen 5's release period where you and I will argue in the most friendlist of ways of AMD's roadmap. We did it the last 2 times.
Hulk
Diamond Member
- Oct 9, 1999
- 5,140
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8+8 ADL and 8+16 RPL and the hybrid approach in general has worked out well for Intel. Before you jump on me let me explain.
I'm just doing some Friday night random rambling here...
Intel is/was behind in process technology. The reality of this means they simply cannot afford the transistor count that AMD can with TMSC and have the resulting part make economic sense.
Now let me be clear here. Intel decided to put power efficiency on the back burner in favor of area efficiency. There is no free lunch, choices have to be made.
So they relied on the fact that many applications fall into two categories:
Category 1 include the application that rely on ST performance and only utilize a handful of cores. Games, DAW's, and many applications today still only really use 6, maybe 8 cores. The proof of this is that ADL and RPL with only 8 P cores compete well against AMD and their 16 core parts in to many applications. What's the ideal number of P cores? TBD. But I do know a core with 50 E cores would get smashed by AMD in most applications that aren't ridiculously threaded applications. Is 4 enough? Maybe. 6 might be where the market is now if Intel can dig another 15 or 20% IPC out of Raptor Cove.
The point is that as software MT gets better and better the need for the P core numbers decreases.
Category 2 are the applications that will load every core available like rendering and come encoding algorithms. So there is a need for the E cores in order to be competitive with these applications.
Now here's something to think about. What if many of these applications score just as well with 6 P cores as with 8P's?
This would lead one to the conclusion that if you took the transistors available for the P's and fabbed 6 P's, which use the same area but have more transistors than the 8P's, these new P's would have higher IPC and better overall performance than the 8P part where 2 or 3 of the P's are not getting loaded often.
In addition if the 16E's could see a big lift in IPC, say 25%, then we could see a reason for reducing the P count.
The BIG question here is how current software is distributed in terms of MT.
Made up numbers
10% of applications use 2 or less threads.
40% of applications use 3-4 threads.
25% of applications use 5-6 threads.
15% of applications use 7-8 threads.
5% of applications use 9-12 threads.
5% of applications will load every thread available.
So Intel would need to do some work to figure out what these numbers actually are and build chips to fit the curve.
AMD on the other hand can sit back on their superior process technology and just make 16P parts that for the moment fit the market will without any hybrid complexities and idiosyncrasies. Or perhaps it should be "idosyn crazies!"
I'm just doing some Friday night random rambling here...
Intel is/was behind in process technology. The reality of this means they simply cannot afford the transistor count that AMD can with TMSC and have the resulting part make economic sense.
Now let me be clear here. Intel decided to put power efficiency on the back burner in favor of area efficiency. There is no free lunch, choices have to be made.
So they relied on the fact that many applications fall into two categories:
Category 1 include the application that rely on ST performance and only utilize a handful of cores. Games, DAW's, and many applications today still only really use 6, maybe 8 cores. The proof of this is that ADL and RPL with only 8 P cores compete well against AMD and their 16 core parts in to many applications. What's the ideal number of P cores? TBD. But I do know a core with 50 E cores would get smashed by AMD in most applications that aren't ridiculously threaded applications. Is 4 enough? Maybe. 6 might be where the market is now if Intel can dig another 15 or 20% IPC out of Raptor Cove.
The point is that as software MT gets better and better the need for the P core numbers decreases.
Category 2 are the applications that will load every core available like rendering and come encoding algorithms. So there is a need for the E cores in order to be competitive with these applications.
Now here's something to think about. What if many of these applications score just as well with 6 P cores as with 8P's?
This would lead one to the conclusion that if you took the transistors available for the P's and fabbed 6 P's, which use the same area but have more transistors than the 8P's, these new P's would have higher IPC and better overall performance than the 8P part where 2 or 3 of the P's are not getting loaded often.
In addition if the 16E's could see a big lift in IPC, say 25%, then we could see a reason for reducing the P count.
The BIG question here is how current software is distributed in terms of MT.
Made up numbers
10% of applications use 2 or less threads.
40% of applications use 3-4 threads.
25% of applications use 5-6 threads.
15% of applications use 7-8 threads.
5% of applications use 9-12 threads.
5% of applications will load every thread available.
So Intel would need to do some work to figure out what these numbers actually are and build chips to fit the curve.
AMD on the other hand can sit back on their superior process technology and just make 16P parts that for the moment fit the market will without any hybrid complexities and idiosyncrasies. Or perhaps it should be "idosyn crazies!"
Yes exactly. Launching a completely new platform with new socket and chipset combined with a 6+8 CPU that can't beat the old gen, I don't think this is appealing. 6+8 is not even a sidegrade to 8+16 like CML-S to RKL-S. They have to delay MTL-S into H2 2024 or whenever ARL-S comes if they have to (assuming MTL-S isn't fully cancelled).
I doubt they'll fully cancel MTL-S. Not without an ARL-S on Intel fabs, at any rate. They're surely paying a premium for those N3 wafers, and they'll want as much of the market as possible on the far cheaper MTL silicon. I bet 15th gen will use MTL up to i5 (except K), and ARL for K series i5s through i9.
DrMrLordX
Lifer
- Apr 27, 2000
- 22,912
- 12,983
- 136
LOL
I've basically given up on their roadmaps. Zen5 is far enough out that it will come out . . . whenever. It would be funny if it hits before Granite Rapids, though. Like imagine Emerald Rapids having to face off against Turin.
So far no 4S or 8S SPR Have been spotted yet, those could be ready early 2024
Dell has announced 960/860 which uses 4S. https://www.servethehome.com/new-de...intel-xeon-scalable-sapphire-rapids-launched/
These are rather niche but available for specific customers who need beefy servers with specific RAS features.
Edit: supermicro as well. https://www.supermicro.com/en/products/superblade . 8U supports 4 socket servers.
That guy is impressed with Xeon W9 3495X GFLOPS Performance on HPCG on Linux.
I am more impressed that a single 32 Core Genoa 9374F is as fast.
Hxl said something about q4 23 for ER. Intel needs a core design that's on par with Zen's. Zen only needs 16 cores at the top to do what it can do on the consumer level stuff, Intel needs 24 cores. Intel is at a major loss with their power use and the lack of operable ht on their e's.
That's a weird comparison. Those E cores only take ~1/4th the area of the P cores. And the whole thing is at a full node disadvantage. The E cores don't need SMT to be competitive.
Plans probably changed.
I seriously doubt MTL & ARL will be on the 'same' 'gen' considering some rumours have a big ST increase between the two architectures. I think Intel has ARL-S on TSMC N3 for the CPU tile so they can release it sooner than later.
But if ARL-S is on TSMC N3 being able to come 1H of 2024 close to Zen 5 and MTL-S struggles to hit 5Ghz even by the end of the year in the labs what's the point
The biggest screwup in all of this is that Z890 looks damn great as a platform with Wifi 7, 20 PCI-e Gen 5.0 slots (enough for 99% of DIYers) and seemingly could be upgradeable to Panther or even Nova Lake, damning for Intel was not able to do at least a 8+8 i7 MTL-S SKU this year because a 5.1Ghz 8P i7 would be amazing with 6400 MT/s dies that can do like 8800 MT/s CL32 for exampl if it came out as planned and able to compete properly against Zen 4 V-Cache.
What are the Chances of this being Emerald Rapids? The board is 2 socket, but the L3 Cache is 3.75 MiB per Core
I'm suspicious, if nothing else. Not entirely sure how to parse the CPUID, but that is just matching SPR, right? And "Stepping 3"? I'd expect EMR to be A0 or A1 around now.
I agree it makes for an awkward lineup and branding, but Intel's only alternative would be to launch 14th gen and 15th gen desktop simultaneously, which would be confusing in its own right. My bet is we'll see 14th gen launch as a combo of MTL mobile parts and RPL refreshes for filler, and then 15th gen as LNL (premium mobile), ARL (mobile and higher end desktop), and MTL (low end desktop).
They may have just disabled some cores for some reason. 450 MB L3 matches the full amount of 2 dual cpus.
Do you mean Quad CPU System(4S), I was thinking that too, but the Motherboard is only a 2 socket board
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