You are arguing that you can increase the distance between transistors (decreasing density) but putting less transistors means transistor density increases. Please show me how the math works out on that.
Intel has nothing to worry about from AMD re: awkward branding, after seeing AMD notebook model numbers.
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Yes, COAG allows you to decrease the cell height and increase density if the design allows for it. However, this was introduced with the original 10 nm in Cannon Lake and was part of their density increase claim over their 14 nm process.
This was not new for 10SF. It was in Cannon Lake.
I think it's improvements to COAG. Afterall, 10SF didn't just deal with gate pitch.
Gate pitch isn't everything...
Quoting Intel;
"In an email to IT World Canada, Intel explained that while the gate pitch impacts the size of the standard cell, it’s only a small part of the various factors that affect density. Design choices, metal routing layers, and many other factors all determine transistor density. Additionally, Intel said that “On the whole, our 10nm SuperFin technology is equivalent in density to foundry 7nm processes.”
"In an email to IT World Canada, Intel explained that while the gate pitch impacts the size of the standard cell, it’s only a small part of the various factors that affect density. Design choices, metal routing layers, and many other factors all determine transistor density. Additionally, Intel said that “On the whole, our 10nm SuperFin technology is equivalent in density to foundry 7nm processes.”
What improvements could you add to COAG to allow for higher density that would allow you to increase density?
Gate pitch isn't everything. For example, there's required dummy gates (which Intel decreased but again, was introduced with the original 10 nm process). However, there is no indication that Intel did anything except decrease density.
There is no indication Intel decreased density.
They increased gate pitch, but also worked on other parts of the transistor.
I admitted I was wrong that Intel increased density with SF, I obviously misread that quote
But saying Intel decreased density is wrong as well.
Intel claimed with OG 10nm that they were equivalent to external 7nm
And they continued to claim they were equivalent to external 7nm after SF as well (in density).
Quoting Intel;
"In an email to IT World Canada, Intel explained that while the gate pitch impacts the size of the standard cell, it’s only a small part of the various factors that affect density. Design choices, metal routing layers, and many other factors all determine transistor density. Additionally, Intel said that “On the whole, our 10nm SuperFin technology is equivalent in density to foundry 7nm processes.”
I don't think this quote is supporting your stance like you think it is. Remember, Intel originally claimed higher density for 10 nm compared to foundry 7 nm processes. Now they are saying it is, "equivalent".
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Originally Intel claimed over 100 MTr/mm2, which was the highest in the world at the time.
Here is an article analyzing the various nodes from different foundries. They give this one line comparison between 10nm and 10nm+
Also, just to address the following since you never actually went back and tried a realistic calculation:
In your example, if you increase gate pitch, thus decreasing density say 10%, you would get 80 transistors in 8.8 mm2. Your transistor density would drop to 9 transistors per mm2 but your overall area would still go down 12%. Thus, decreasing density leading to using less buffers actually allows you to use less area overall which is what the Anandtech article was saying.
I don't think you will find any real analysis that comes to the opposite conclusion. With that, I'm really out for this topic. Like I said, believe what you like, I don't care. We'll see how/when Intel 4 and 20a land.
Apparently Intel was claiming their 10nm was better than TSMC's 7nm as late as 2021, and they would have been on SF at that point (not yet ESF either)
And I don't think Intel ever said their 10nm was "better" than TSMC 7nm, despite their original density numbers being reported to be <10% higher
But by the time that quote rolled around in 202, TSMC 7nm with EUV surpassed Intel 10nm density by <10% as well for HD cells
The problem is there literarily is no real analysis that indicates that Intel 10SF decreased density, at the very least by no significant margin,
since Intel has consistently claimed their 10nm was as good as external 7nm, before or after SF, for density.
Gate pitch might have increased sure, but Intel also claimed they worked on numerous other parts of the transistor as well.
But ye, we will see where Intel 4 and Intel 20A land...
But pushing a more interesting leak back to the forefront of this thread, rather than discussion on 10nm;
GNR and SRF
GNR and SRF
Hulk
Diamond Member
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If Intel plans on using all of the even numbers below 20 they'll have a whole lot of "new" nodes that used to be "+" nodes. Good for them to bend reality as they see fit.
We're all living in the Matrix anyway.
We're all living in the Matrix anyway.
By 2025, MTL should only make sense for very cost sensitive markets. They should have ARL on 20A to fill in for mobile, and maybe we'll even see it in desktop eventually? And if nothing else, they will want to push 20A ARL out in as high a volume as possible as a proof point for their fabs. And hopefully by the end of 2025, we see something (Cougar Cove?) on 18A across the board.
ARL also has a secret that will make the SKU choices even more interesting. But regardless, I think they'll just have to live with the generational gap in performance between the i5 and i7. It'll be a mess, but unless they introduce a downmarket ARL die, they don't have much of a choice. Hopefully that's temporary, however, because even just from a DIY perspective, there won't be a value champ like the 12400 from that lineup.
An Amateur's Project:
A fun mockup of the EMR core (GLC++? haha) based on 5MB L3 EMR rumors:
On the left we have the mockup of a 5MB L3 EMR core, on the right we have the current SPR core.
Method:
So the current SPR has 1.875MB of L3 per core. This is divided into 2 L3 cache arrays, which are slightly differently sized. By adding the two areas together, and then dividing 1.875/total area, we can find MB/area.
Multiply this by the area of each of the data arrays to find how much each array holds, and we get how much cache each data array holds.
I then replicated the blocks in a method that seemed area efficient and continued to hold a 'square' or 'rectangle' shape for the core, as well as leaving space for extra control for the cache.
Conclusion for core:
It looks like the core size grew by ~20%. While there is some extra space in between some of the blocks, I probably underestimated the amount of space needed for L3 control as well as Mesh Agent, as I suspect that would probably grow a bit in EMR from the extra L3 cache and in order for that to better communicate between cores.
What about the CPU?
The "core" part of one of the SPR CPU tiles (including the memory control tile) is only slightly larger than 50% of the tile.
Increasing that by 20% means that the total tile is only ~10% larger than the SPR tile. For more than 2.5X the L3 cache per core, an only ~10% additional die size does not sound that bad. Especially since, from chips and cheese testing, SPR's major bottleneck seems to be the L3 cache.
64 cores?
If we look at the core configurations for SPR, we see a 4 x 4 array of cores, with a memory control tile in the mix. For SPR, the max is 60 cores, so for EMR reaching 64 cores, the configuration of the cores have to have been changed.
I see two options here: a 4 x 4 array of cores, with the memory control tile moved off the array closer to where the DDR5 PHY or Accerelators and PCIE or CXL blocks are or....
a new configuration. 5 x 4? 6 x 3?
Here's a mockup of a potential 5 x 4 configuration:
The problem with Intel implementing a potential new configuration of cores is that it would most likely take longer to design, and have to disable 2 or 3 cores (if it stays on one memory controller per tile) for the 64 core max rumors to be true. The Tile also grows by closer to 15-20%.
So ye, that's pretty much it
A fun mockup of the EMR core (GLC++? haha) based on 5MB L3 EMR rumors:
On the left we have the mockup of a 5MB L3 EMR core, on the right we have the current SPR core.
Method:
So the current SPR has 1.875MB of L3 per core. This is divided into 2 L3 cache arrays, which are slightly differently sized. By adding the two areas together, and then dividing 1.875/total area, we can find MB/area.
Multiply this by the area of each of the data arrays to find how much each array holds, and we get how much cache each data array holds.
I then replicated the blocks in a method that seemed area efficient and continued to hold a 'square' or 'rectangle' shape for the core, as well as leaving space for extra control for the cache.
Conclusion for core:
It looks like the core size grew by ~20%. While there is some extra space in between some of the blocks, I probably underestimated the amount of space needed for L3 control as well as Mesh Agent, as I suspect that would probably grow a bit in EMR from the extra L3 cache and in order for that to better communicate between cores.
What about the CPU?
The "core" part of one of the SPR CPU tiles (including the memory control tile) is only slightly larger than 50% of the tile.
Increasing that by 20% means that the total tile is only ~10% larger than the SPR tile. For more than 2.5X the L3 cache per core, an only ~10% additional die size does not sound that bad. Especially since, from chips and cheese testing, SPR's major bottleneck seems to be the L3 cache.
64 cores?
If we look at the core configurations for SPR, we see a 4 x 4 array of cores, with a memory control tile in the mix. For SPR, the max is 60 cores, so for EMR reaching 64 cores, the configuration of the cores have to have been changed.
I see two options here: a 4 x 4 array of cores, with the memory control tile moved off the array closer to where the DDR5 PHY or Accerelators and PCIE or CXL blocks are or....
a new configuration. 5 x 4? 6 x 3?
Here's a mockup of a potential 5 x 4 configuration:
The problem with Intel implementing a potential new configuration of cores is that it would most likely take longer to design, and have to disable 2 or 3 cores (if it stays on one memory controller per tile) for the 64 core max rumors to be true. The Tile also grows by closer to 15-20%.
So ye, that's pretty much it
Don't be afraid to think outside the box a little
. Literally, in this case.
Hulk
Diamond Member
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Based on Intel's recent history with 14nm and 10nm I don't think they do just 1 generation on Intel 4 for a couple reasons.
First, I would be astounded if ARL was ready to go on the desktop in 2025 on 20A. 20A will hold them up.
Second, in order to avoid a Rocket Lake fiasco (backport to Intel 4 for ARL) Intel will keep ARL on 20A, this means when 20A inevitably falls behind schedule that will leave them with MTL refresh on a tweaked Intel 4, maybe they'll rename it "Intel 3. Maybe that's whey they saved numbers between Intel 4 and 20A.
So what I'm predicting is Raptor Refresh and maybe MTL mobile 2023. MTL desktop and mobile (again) on the refined Intel 4 desktop node in 2024.
ARW 20A mobile only 2025.
Uh, Intel 3 is officially a thing...
I think it's reasonably likely that we only see ARL-P 20A devices on shelves in 2025, but they should hopefully be able to move quickly and fill out the lineup. Maybe have some 18A chips in time for the holidays.
DrMrLordX
Lifer
- Apr 27, 2000
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I don't think even MLID went so far as to claim that it was cancelled entirely. His claim (which can not be verified, and may never be verified due to the nature of the product) was that the high core-count variants of Sierra Forest (AP) were gone, while the lower-core count versions were being forced out the door ASAP to fill the orders of a select customer "on time" (by Q2 2023, if I recall the leak correctly. Honestly I don't want to go back down his rabbit hole to look).
uzzi38
Platinum Member
- Oct 16, 2019
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I wouldn't be quite so sure about that. There's the rumor it was revived as a sort of dual-SP die setup. And looking at that image, the copyright is from 2023. Can't be that old.
I certainly think this is legit. Lots of interesting details to dissect.
- Up to DDR5-6400 for 1 DIMM per channel.
- MCR support confirmed, up to an effective 8000MT/s (hope this eventually trickles down to HEDT...)
- Self-Boot == no chipset required?
- Goes up to at least 500W.
IntelUser2000
Elite Member
- Oct 14, 2003
- 8,686
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I don't fully agree with this either. Look at this slide.
The plusses are just that, nice improvements but small. 5.5%, 3.8%, 5.8%, 5.9%. And it's not multiplicative either, it's additive. 10nm SF wasn't called a + because it single handedly brought improvements equal to four plusses.
Let's look at Intel 3 and 18A shall we?
Intel 4 - 20%
Intel 3 - 18%
Intel 20A - 15%
Intel 18A - 10%
The performance gains are big. Interestingly in this aspect 20A is LESS than the Intel 3 process. More work for less gains, this is the slow death of Moore's Law.
While we heavily focus on density, performance is very important. TSMC's 20nm brought great density gains, but almost no one used it, and they waited for 16nm with FinFET. Likewise TSMC's N2 brings barely any density gain, but performance seems good. Probably is going to be similar with Intel's 20A. It's about performance not density. We used to get both readily but that ship is slowly sailing away.
And you are also forgetting that Intel 3 is being skipped on client, but Intel 4 is being skipped on server. That's why there's a gap. They aren't changing names, they are skipping processes.
You got a lot to learn buddy. Thinking buffers aren't made of transistors haha. Buffers are basic building blocks. Not logic, but important.
If anything, the SF and ESF(called Intel 7 now) are less dense than 10nm in Icelake. The clock speed increase didn't come for free. Yes, pitches did increase. And pitches are one thing that directly affects density, unlike things like COAG which is a maybe.
We know the whole 14nm/10nm density claim was quite misleading since while it could be true, it did not apply to their Core lines. Atom gained awesomely and so did their GPUs. But that's not bringing them much money do they? They tried to do a mobile shift in 14nm, but they were in essence killing the hen that lays golden eggs(just like the story to get more of them inside her).
Very interesting. About ARL+MTL, little bit of price adjustments and plus or minus 100MHz adjustments and P+E core ratios can easily make it work.
@Hulk If they do as you planned, then they'll lose on desktop again. I personally am not that pessimistic. They know that Arrowlake, even in small volumes at the high end is necessary to charge extra at the high end, because that's where the margins and profits are. If Meteorlake is at top, then you end up at x600K, and maybe x700K at max. That's a loss.
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