Discussion Intel current and future Lakes & Rapids thread

[uzzi38]

You would have to wonder what the difference between the I9 and I5 skus are going to be then, if ARL is i7 and i9, and MTL is i5 and below.

I would imagine the split is more like the RPL/ADL split we have right now.

 

[IntelUser2000]

Throwing something out there. Based on the current leaks/situation,

2023 H2 - Raptorlake-S Refresh for desktop

2023 H2(a bit later maybe) - Meteorlake mobile. Personally I am expecting 9-15W U chips(maybe even lower), not the -Ps here.

Late 2023 - Emerald Rapids 1-2S for server

Jan 2024 - Meteorlake-P for mobile

Spring 2024 - Granite Rapids for 4-8S for server and Sierra Forest for cloud server

Also Spring 2024 - Arrowlake-S for high end desktop, and Meteorlake-S for low to mid-end desktop

Fall 2024 - Lunar Lake for low power chips under 15W.

2024 Late - Granite Rapids 1-2S for Server

Jan 2025 - Arrowlake-P on Intel 20A for mobile.

If we continue then...

Spring 2025 - Arrowlake-S Refresh across the line on 20A for Desktop
Summer 2025 - Diamond Rapids 4-8S for Server, and Forest successor on 18A
Fall 2025 - 18A Panther Lake for ultra low power -Y and -U
Late 2025 - Diamond Rapids 1-2S for Server
Jan 2026 - 18A Panther Lake higher power -U -P, and -H
Spring 2026 - 18A Panther Lake-S for Desktop

Thoughts: Interestingly I see some connection between Meteorlake mobile for later this year and Lunar Lake. The split relation it has with it's brothers is also common between them. Intel obviously sees the need for lower power chips that are more dedicated(or better) at task than what they currently have.

And Raptorlake does not have <15W chips at all, bringing the possibility of having Meteorlake come earlier, otherwise it would have had to be all Q1 2024. I originally expected Meteorlake 5W to be the only contender, because I fully expected they'd continue with 9-15W on Raptorlake, yet they have decided not to do so.

Mobile cannot have less than a year lifespan, so they are just cutting parts of it out in Raptorlake and get Meteorlake out faster instead.

Arrowlake-S needs to be towards later 2024 if they want to be in 20A, but that makes them not competitive, so it goes on TSMC N3, and further refinements come later. Arrowlake and 20A may be similar to Intel 4 in that fact that it's a transitional product meant to fill the gap and only plays a limited role.

I think it's also possible Lunar Lake is more towards middle of 2024 than end, which means 20A is rather early too. Hence the rumors of TSMC again. And in 2025-2026 18A comes with Panther Lake to replace all.

2021-2022 Intel 7 to 2025-2026 Intel 18A: "5 nodes in 4 years"

 

[Geddagod]

We know the whole 14nm/10nm density claim was quite misleading since while it could be true, it did not apply to their Core lines. Atom gained awesomely and so did their GPUs. But that's not bringing them much money do they? They tried to do a mobile shift in 14nm, but they were in essence killing the hen that lays golden eggs(just like the story to get more of them inside her)

Based on the fact that that the atom cores in Meteor Lake seemed to scale pretty much the same (slightly better) as Redwood Cove cores, I don't think the Atom cores scaled any better on their nodes.
If Atom were based on HD, the scaling would be a lot worse than the Core lines based on HP.
And their density claims did apply to the iGPU blocks, just not the whole CPU... literarily like any design.
What was TSMC 'misleading' since zen 2 and zen 3 CCD density were similar to a quadcore icelake CPU? Or is the fact that they released some Apple mobile chips with closer to theoretical max density save their skin?

 

[Geddagod]

I would imagine the split is more like the RPL/ADL split we have right now.

RPL/ADL IPC are way closer than what MTL and ARL are rumored to be.
The only way they would be comparable would be if Lion Cove either is just GLC++++ (highly doubtful) or if RWC is a new architecture and Lion Cove is RWC+. (also doubtful).

 

[Geddagod]

Don't be afraid to think outside the box a little . Literally, in this case.

You don't think the mesh is a square?
I mean if the silicon between the 24X UPI and the top left corner core is 'dead silicon' I suppose you could increase the vertical space between them a bit and maybe cram a core in there to reach 16 per tile...
But that's all I got in guesses haha

 

[Redfire]

You don't think the mesh is a square?
I mean if the silicon between the 24X UPI and the top left corner core is 'dead silicon' I suppose you could increase the vertical space between them a bit and maybe cram a core in there to reach 16 per tile...
But that's all I got in guesses haha

That bit of silicon is used for GPIO, stuff like USB.

 

[Geddagod]

I certainly think this is legit. Lots of interesting details to dissect.

• Up to DDR5-6400 for 1 DIMM per channel.
• MCR support confirmed, up to an effective 8000MT/s (hope this eventually trickles down to HEDT...)
• Self-Boot == no chipset required?
• Goes up to at least 500W.

Also, wow, 20 layer PCB. That must cost a pretty penny.

Prob the most interesting part about this IMO is power draw.
Ignoring connectivity costs for now...
SPR gets 350/60 = 5.83 watts per core
And GNR should get 500/128 = 3.91 watts per core
But because the interconnect should be way bigger for GNR, I expect the relative value should be even lower considering the larger overhead, and also from having to connect to more physical tiles as well for across tile communication.
A less than 33% reduction in power/core.

If you look at the AMD side of things, it doesn't look like their power/core moves down much from like ~4.0-4.5 watts per core (with connectivity + IO in mind so less than that) despite architecture changes and node shrinks
And Turin having the same core count but reaching a 600W TDP (20% more) makes little sense in comparison, unless
A) the power/frequency scaling for Zen 5 is really good
B) the interconnect cost for Turin is relatively high (afterall they use way more chiplets, and I'm pretty sure iFOP is less efficient than EMIB)
C) Could be additional accelerators on Turin that cause extra power consumption?
D) RWC+ is more efficient than Zen 5 (doubt) or IPC is higher, so they can clock less
E) Intel 3 is marginally to a full node superior to TSMC N4
Or it could be some combination of such.

It makes little sense to me, IMO, that if GNR and Turin have the same core count, and GNR only has marginally worse IPC than Turin, and ends up being only marginally worse in total MT performance, why Intel would decide to potentially kneecap their competitiveness by then only limiting their power draw to 500W.
I also believe both companies have a relative idea of where they are relative to eachother and where they would be relative to eachother in terms of performance.
I don't think it's a coincidence that SPR was planned to be a Milan competitor and come out with 60 cores.
And I don't think it's a coincidence that Intel mockups in their own presentations, along with leaks, were showing 96 cores split in 2 Tiles for GNR when it was on Intel 4 and coming out in 2023, and supposed to release against Milan.
And lastly, I still don't think it's a coincidence that both GNR and Zen 5 are rumored to have similar, if not the same core counts.

 

[Geddagod]

Of course, all of this would be moot if max TDP for GNR also hits 600 watts, but I'm desperate for any tidbits for GNR LOL

 

[Hulk]

I don't fully agree with this either. Look at this slide.

https://images.anandtech.com/doci/15971/Section%201%20%2821%29.jpg

The plusses are just that, nice improvements but small. 5.5%, 3.8%, 5.8%, 5.9%. And it's not multiplicative either, it's additive. 10nm SF wasn't called a + because it single handedly brought improvements equal to four plusses.

Let's look at Intel 3 and 18A shall we?

Intel 4 - 20%
Intel 3 - 18%
Intel 20A - 15%
Intel 18A - 10%

@Hulk If they do as you planned, then they'll lose on desktop again. I personally am not that pessimistic. They know that Arrowlake, even in small volumes at the high end is necessary to charge extra at the high end, because that's where the margins and profits are. If Meteorlake is at top, then you end up at x600K, and maybe x700K at max. That's a loss.

Thanks for responding but I have some questions/comments.

1. As for the list of "on the horizon" Intel nodes, we don't currently have any actual, physical chips using these nodes so all numbers are simply what Intel is telling us. I'm thinking I can find similar hyper before 14nm was available, or 10nm for that matter as well. However, if they are comparing the performance of the final node for each process and there are inter "+'s" then those numbers seems quite reasonable as I posted a comparison of Intel nodes using max clocks of each Intel node. But on the other hand, with 14nm and 10nm, we're looking at 4+ years from first release to final release. That's a long time. If you think about it if Intel 4 is released in 2023, if Intel stays on their actual release timeline for the last 2 nodes it'll be 2027 (perhaps later) before they make their next node update. In summary I don't see these nodes being back-too-back in terms of years, history tells us it's closer to half-decades and that is not a joke. That is why I'm pessimistic on their release schedule.

2. What is the criteria that differentiates a new node from a +?

 

[Geddagod]

2. What is the criteria that differentiates a new node from a +?

Density.

 

[Geddagod]

plusses are just tweaks on an existing node, new nodes are more major changes to the transistor itself
honestly, tweaks from plusses or sub nodes from both TSMC and Intel look to bring decent gains in perf/watt if anything, even relative to a full node shrink, but won't have nearly the same impact on density.

 

[Redfire]

2. What is the criteria that differentiates a new node from a +?

There is no fixed guideline for that really. It just depends on how your marketing wants to spin it.
A "node" doesn't have a fixed meaning, much like the numbers mean nothing.

 

[Henry swagger]

If Intel plans on using all of the even numbers below 20 they'll have a whole lot of "new" nodes that used to be "+" nodes. Good for them to bend reality as they see fit.
We're all living in the Matrix anyway.

All the foundries are lying.. density and high drive current matter not these fake nm numbers

 

[Henry swagger]

Based on the fact that that the atom cores in Meteor Lake seemed to scale pretty much the same (slightly better) as Redwood Cove cores, I don't think the Atom cores scaled any better on their nodes.
If Atom were based on HD, the scaling would be a lot worse than the Core lines based on HP.
And their density claims did apply to the iGPU blocks, just not the whole CPU... literarily like any design.
What was TSMC 'misleading' since zen 2 and zen 3 CCD density were similar to a quadcore icelake CPU? Or is the fact that they released some Apple mobile chips with closer to theoretical max density save their skin?

Both p and e cores use high performance cells on raptor lake

 

[mikk]

Intel Raptor Lake Refresh Desktop CPUs Rumored To Launch In August 2023

Intel's Raptor Lake refresh desktop CPUs which were recently leaked are now rumored to launch in the third quarter of 2023.

wccftech.com

If Raptor refresh comes in August it could mean ARL-S might come in August 12 months later? Or let's say Q3 2024. Alder Lake to Raptor Lake gap was ~12 months.

 

[Geddagod]

Intel Raptor Lake Refresh Desktop CPUs Rumored To Launch In August 2023

Intel's Raptor Lake refresh desktop CPUs which were recently leaked are now rumored to launch in the third quarter of 2023.

wccftech.com

If Raptor refresh comes in August it could mean ARL-S might come in August 12 months later? Or let's say Q3 2024. Alder Lake to Raptor Lake gap was ~12 months.

Intel showed it can launch a new desktop product within 1/2 a year of the previous product with RKL.
It all depends on when TSMC 3nm ramps for Intel IMO. I haven't heard anything suggesting ARL development is being seriously delayed or anything, though you prob want to ask Exist on that as I don't have any sources or anything like that.
I would expect 2H 2024 as well though for ARL-S.

 

[Hulk]

Intel Raptor Lake Refresh Desktop CPUs Rumored To Launch In August 2023

Intel's Raptor Lake refresh desktop CPUs which were recently leaked are now rumored to launch in the third quarter of 2023.

wccftech.com

If Raptor refresh comes in August it could mean ARL-S might come in August 12 months later? Or let's say Q3 2024. Alder Lake to Raptor Lake gap was ~12 months.

That would be great. but isn't ARL designed for Intel 20A? But you also have to keep in mind that Intel has never released a new node in 12 months from the last node. Closest they ever came in recent history was 120nm to 90nm, that was 13 months.

But if you look at more recent releases...

45nm to 32nm - 26 months
32nm to 22nm - 27 months
22nm to 14nm - 16 months (mobile only Broadwell release more like 26 months to 14nm on the desktop with Skylake)
14nm to 10nm - 57 months.

10nm to Intel 4 is 42 months and counting.

So if ARL is 20A we're looking at 3 or 4 years based on past history.

 

[Geddagod]

~10% Avrg FPS gain from eDRAM L4 in the 5775C, tested with 16GB of DDR3 2400 (and while I don't know much about DDR3, this seems pretty good) tested across 10 games.

 

[Hulk]

~10% Avrg FPS gain from eDRAM L4 in the 5775C, tested with 16GB of DDR3 2400 (and while I don't know much about DDR3, this seems pretty good) tested across 10 games.

Crystal Well was a cool feature of Broadwell and like today the extra cache helped with games.

 

[mikk]

That would be great. but isn't ARL designed for Intel 20A?

They can use TSMC 3nm.

 

[Geddagod]

They can use TSMC 3nm.

very curious too see if they end up using HP cells as the STRD cell in their TSMC designs too.
I really don't think they have too this time around, ARL-S at worst should have node parity with Zen 5, and more likely a full node advantage.

 

[Hougy]

Originally Intel claimed over 100 MTr/mm2, which was the highest in the world at the time.

Here is an article analyzing the various nodes from different foundries. They give this one line comparison between 10nm and 10nm+




Also, just to address the following since you never actually went back and tried a realistic calculation:



In your example, if you increase gate pitch, thus decreasing density say 10%, you would get 80 transistors in 8.8 mm2. Your transistor density would drop to 9 transistors per mm2 but your overall area would still go down 12%. Thus, decreasing density leading to using less buffers actually allows you to use less area overall which is what the Anandtech article was saying.

I don't think you will find any real analysis that comes to the opposite conclusion. With that, I'm really out for this topic. Like I said, believe what you like, I don't care. We'll see how/when Intel 4 and 20a land.

What's a buffer and what is it used for?

 

[Exist50]

You don't think the mesh is a square?
I mean if the silicon between the 24X UPI and the top left corner core is 'dead silicon' I suppose you could increase the vertical space between them a bit and maybe cram a core in there to reach 16 per tile...
But that's all I got in guesses haha

To be just a little more cryptic, you're making a reasonable, but ultimately incorrect assumption, perhaps without even realizing it is an assumption. But hopefully they won't keep us all waiting and actually show it sooner rather than that later.

That bit of silicon is used for GPIO, stuff like USB.

GPIO is its own thing. USB would be separate.

 

[Doug S]

What's a buffer and what is it used for?

The short answer is it is a current amplifier used for impedance matching between circuits or for long wire runs. It is more complicated than that as there multiple buffer types and some may amplify voltage rather than current, but that's the simplest way to explain it that covers most cases.

 

[Exist50]

The short answer is it is a current amplifier used for impedance matching between circuits or for long wire runs. It is more complicated than that as there multiple buffer types and some may amplify voltage rather than current, but that's the simplest way to explain it that covers most cases.

Yeah, current amplifier doesn't really work in this particular case. I'd just leave it at saying that it boosts the signal without changing its value. Commonly implemented as just a pair of inverters.