But overall area also decreased, along with the number of transistors. The growth of the gate pitch might have been minor, or could have been major, but overall if the % increase in area decreasing outpaced the %# transistor, density would grow.
I agree it makes for an awkward lineup and branding, but Intel's only alternative would be to launch 14th gen and 15th gen desktop simultaneously, which would be confusing in its own right. My bet is we'll see 14th gen launch as a combo of MTL mobile parts and RPL refreshes for filler, and then 15th gen as LNL (premium mobile), ARL (mobile and higher end desktop), and MTL (low end desktop).
View attachment 78405
For example, this slide literally states improved transistor density from COAG.
This slide from Intel 10SF literarily says improved transistor density.
I think it's improvements to COAG. Afterall, 10SF didn't just deal with gate pitch.Yes, COAG allows you to decrease the cell height and increase density if the design allows for it. However, this was introduced with the original 10 nm in Cannon Lake and was part of their density increase claim over their 14 nm process.
I think it's improvements to COAG. Afterall, 10SF didn't just deal with gate pitch.
Gate pitch isn't everything...
There is no indication Intel decreased density.What improvements could you add to COAG to allow for higher density that would allow you to increase density?
Gate pitch isn't everything. For example, there's required dummy gates (which Intel decreased but again, was introduced with the original 10 nm process). However, there is no indication that Intel did anything except decrease density.
Quoting Intel;
"In an email to IT World Canada, Intel explained that while the gate pitch impacts the size of the standard cell, it’s only a small part of the various factors that affect density. Design choices, metal routing layers, and many other factors all determine transistor density. Additionally, Intel said that “On the whole, our 10nm SuperFin technology is equivalent in density to foundry 7nm processes.”
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There is no indication Intel decreased density.
They increased gate pitch, but also worked on other parts of the transistor.
I admitted I was wrong that Intel increased density with SF, I obviously misread that quote
But saying Intel decreased density is wrong as well.
Intel claimed with OG 10nm that they were equivalent to external 7nm
And they continued to claim they were equivalent to external 7nm after SF as well (in density).
Ice Lake is based on Intel’s 10nm+ Node and its density is significantly lower than that of 10nm used for Cannonlake.
A scenario to show case this:
100 transistors in 10 mm^2, 50 of them are buffers , 10 transistors per mm^2
80 transistors in 8 mm^2, 30 of them are buffers, 10 transistors per mm^2
Density is number of transistors and area.
Apparently Intel was claiming their 10nm was better than TSMC's 7nm as late as 2021, and they would have been on SF at that point (not yet ESF either)I don't think this quote is supporting your stance like you think it is. Remember, Intel originally claimed shigher density for 10 nm compared to foundry 7 nm processes. Now they are saying it is, "equivalent".
The problem is there literarily is no real analysis that indicates that Intel 10SF decreased density, at the very least by no significant margin,I don't think you will find any real analysis that comes to the opposite conclusion. With that, I'm really out for this topic. Like I said, believe what you like, I don't care. We'll see how/when Intel 4 and 20a land.
By 2025, MTL should only make sense for very cost sensitive markets. They should have ARL on 20A to fill in for mobile, and maybe we'll even see it in desktop eventually? And if nothing else, they will want to push 20A ARL out in as high a volume as possible as a proof point for their fabs. And hopefully by the end of 2025, we see something (Cougar Cove?) on 18A across the board.But then I predict that Intel (as usual) will fall in love with the yields that are finally occurring with Intel 4 and 15th generation in 2025 will be a Meteor Lake Refresh that include better, lower voltage mobile parts as well as high clock speed desktop parts.
ARL also has a secret that will make the SKU choices even more interesting. But regardless, I think they'll just have to live with the generational gap in performance between the i5 and i7. It'll be a mess, but unless they introduce a downmarket ARL die, they don't have much of a choice. Hopefully that's temporary, however, because even just from a DIY perspective, there won't be a value champ like the 12400 from that lineup.You would have to wonder what the difference between the I9 and I5 skus are going to be then, if ARL is i7 and i9, and MTL is i5 and below.
Don't be afraid to think outside the box a little64 cores?
If we look at the core configurations for SPR, we see a 4 x 4 array of cores, with a memory control tile in the mix. For SPR, the max is 60 cores, so for EMR reaching 64 cores, the configuration of the cores have to have been changed.
I see two options here: a 4 x 4 array of cores, with the memory control tile moved off the array closer to where the DDR5 PHY or Accerelators and PCIE or CXL blocks are or....
a new configuration. 5 x 4? 6 x 3?
By 2025, MTL should only make sense for very cost sensitive markets. They should have ARL on 20A to fill in for mobile, and maybe we'll even see it in desktop eventually? And if nothing else, they will want to push 20A ARL out in as high a volume as possible as a proof point for their fabs. And hopefully by the end of 2025, we see something (Cougar Cove?) on 18A across the board.
Uh, Intel 3 is officially a thing...that will leave them with MTL refresh on a tweaked Intel 4, maybe they'll rename it "Intel 3. Maybe that's whey they saved numbers between Intel 4 and 20A
I think it's reasonably likely that we only see ARL-P 20A devices on shelves in 2025, but they should hopefully be able to move quickly and fill out the lineup. Maybe have some 18A chips in time for the holidays.ARW 20A mobile only 2025.
assuming Sierra Forrest is cancelled.
It's old. SRF-AP was canned ages ago.View attachment 78398
Anyone know why Harukaze on twitter deleted this? It certainly looks legit.
Also 500 watts on GNR vs 600 watts on Turin?
What's the difference between Intel and AMD TDP again?
I wouldn't be quite so sure about that. There's the rumor it was revived as a sort of dual-SP die setup. And looking at that image, the copyright is from 2023. Can't be that old.It's old. SRF-AP was canned ages ago.
I certainly think this is legit. Lots of interesting details to dissect.View attachment 78398
Anyone know why Harukaze on twitter deleted this? It certainly looks legit.
Also 500 watts on GNR vs 600 watts on Turin?
What's the difference between Intel and AMD TDP again?
This new naming structure allows them to better align with TMSC node "sizes" and allows them to get away from the dreaded "+" syndrome. ie Intel 20A+ will not exist and actually be Intel 18A.
To start of with, TSMC doesn't disclose HCC SRAM density
Intel 7/Intel 10nm is ~7nm.
Intel 10nm HD is ~ 7nm
Intel 7 HP ~ TSMC 7nm
Intel 7 is roughly 15% larger than TSMC 7nm HDC cells
ARL also has a secret that will make the SKU choices even more interesting.