Discussion Intel current and future Lakes & Rapids thread

[A///]

Conflating technical information released at an international academic conference (VLSI) and a planned product roadmap is disingenuous.

VLSID*

 

[A///]

Regarding Intel 4: we know some of its characteristics in the lab and in the limited launch of Loihi2 samples that may or may not have gone to a select few by now. What we don't know is if that node will launch in a suitable state for commercial products until it actually happens.

Meteor Lake is very late to market. It's possible (though not inevitable) that we'll see relaxed features on the final product. Compare unviable 10nm in Cannonlake VS. 10nm+ in IceLake.

If we had had this discussion in early 2017 about the feature sizes of 10nm we might be having the same back and forth. History teaches us that the "real" 10nm was 10nm+ in 2019, and that that node had different feature sizes than those boasted by Intel for 10nm prior to the launch of Cannonlake.

Sorry if this is perhaps redundant.

What was in 2019? Tigerlake or Rocket?

 

[BorisTheBlade82]

Additionally 10nm and 10nm+ didn't have different node dimensions. No idea where people got that info from, I haven't seen it anywhere atleast.
10nm ESF and 10nm had different dimensions, but density overall increased due to it.

If my mind still serves me well, quite the opposite is true. Intel relaxed the density and increased currents in order to make the mess of OG 10nm viable with +, SF and ESF. There are scrutineerings about this on the Internet which I don't have at hand ATM. And this is also the reason why Intel does not publicize Transistor counts anymore.
The already did the same with 14nm.

 

[Geddagod]

If my mind still serves me well, quite the opposite is true. Intel relaxed the density and increased currents in order to make the mess of OG 10nm viable with +, SF and ESF. There are scrutineerings about this on the Internet which I don't have at hand ATM. And this is also the reason why Intel does not publicize Transistor counts anymore.
The already did the same with 14nm.

Never heard of 10nm+ changing anything.
Here's the quote about 10nm SF from Anandtech's article on it:

Normally a larger gate pitch sounds the opposite of what we want for a dense process node technology, however it was explained that in this case making the transistor bigger with improved performance actually means that fewer buffers are needed in the high performance cell libraries, and ultimately the cell size decreases as a result.

So SF actually increased density.
Intel also disclosed transistor counts for SPR, and engineer for SPR said 11 billion transistors IIRC. Idk about alder lake/raptor lake though.

 

[Thunder 57]

Intel is already behind schedule. They completely botched 10nm. Yet some are willing to take everything about Intel 4 at face value? Good luck with that.

Unrelated, there is a now a rumor we will see Arrowlake in Q1 2024? More like MeteorLake. Which will almost certainly never see the light of day on desktops.

I think we need to cool expectations until we start seeing some results.

EDIT

Looks like the actual rumor is that Meteorlake is going away and Arrowlake is being pulled forward to Q1 2024. More believeable, but I have little faith in Intel's execution.

 

[Geddagod]

Intel is already behind schedule. They completely botched 10nm. Yet some are willing to take everything about Intel 4 at face value? Good luck with that.

Unrelated, there is a now a rumor we will see Arrowlake in Q1 2024? More like MeteorLake. Which will almost certainly never see the light of day on desktops.

I think we need to cool expectations until we start seeing some results.

Based on that roadmap, Intel isn't behind schedule.
Intel 4 was stated to be ready for mass production by the end of 2022, and Intel still claims that.
And besides, all the rumors insist that it's not the node that's the issue at this point for why MTL is so delayed, it's the design team.
And again, conflating road maps and the technical size and characteristics of a node is just wrong, since they are completely different.
These aren't expectations or projections, these are the physical size of the cells in the node themselves.
Intel 4 is this. It might have terrible clocks, it might have terrible yields, it might end up never releasing in a real product like OG 10nm.
OG 10nm had the same thing.
But that is the density of the node for it's HP cells.

 

[Thunder 57]

Based on that roadmap, Intel isn't behind schedule.
Intel 4 was stated to be ready for mass production by the end of 2022, and Intel still claims that.
And besides, all the rumors insist that it's not the node that's the issue at this point for why MTL is so delayed, it's the design team.
And again, conflating road maps and the technical size and characteristics of a node is just wrong, since they are completely different.
These aren't expectations or projections, these are the physical size of the cells in the node themselves.
Intel 4 is this. It might have terrible clocks, it might have terrible yields, it might end up never releasing in a real product like OG 10nm.
OG 10nm had the same thing.
But that is the density of the node for it's HP cells.

We're days away from Q2 '24. The earliest we will see Intel 4 appears to be Q4 '24. How is that not behind schedule? And you keep focusing on density as it is the "be all". You even admit OG 10nm was crap. By your logic it should have been awesome because it was supposed to be 2.7x more dense than 14nm.

People, inclusing investors, don't care about density or things like that. They care about performance, margins, etc.

 

[Geddagod]

Intel is already behind schedule. They completely botched 10nm. Yet some are willing to take everything about Intel 4 at face value? Good luck with that.

Unrelated, there is a now a rumor we will see Arrowlake in Q1 2024? More like MeteorLake. Which will almost certainly never see the light of day on desktops.

I think we need to cool expectations until we start seeing some results.

But about ARL, 1H* 2024.
Something very concerning about ARL is that Intel really has not provided us anything on ARL power on, which for a launch 1H 2024, it should happen any time now. If we don't hear anything by the Q1 earnings conference call about power on for ARL, it's pretty much confirmed that it's not going to end up launching in 1H 2024.

 

[Geddagod]

We're days away from Q2 '24. The earliest we will see Intel 4 appears to be Q4 '24. How is that not behind schedule? And you keep focusing on density as it is the "be all". You even admit OG 10nm was crap. By your logic it should have been awesome because it was supposed to be 2.7x more dense than 14nm.

People, inclusing investors, don't care about density or things like that. They care about performance, margins, etc.

Again, Intel never claimed Intel 4 would show up in products by Q2 2022. They said HV manufacturing ready, and Intel still claims Intel 4 is HVM ready.
What is also behind schedule is MTL design/execution team. Raichu claims that it was targeted for a 1H 2023 launch, like I think nearly a year ago, if not more.
But even ignoring rumors, you can see the delays in development when you look at when MTL development schedule:

• MTL taped in end of 1H 2021. slightly less than 2 years after should be the release date. 1H 2023.
• MTL powered on 2Q 2022. ~15 months later, we should see release date. 3Q 2023.

So ye, MTL seems to have been pushed back a quarter or so between tape in and power on, but that could also be a margin of error between development of different products. Until you realize that MTL is still likely not going to end up launching until the very end of 2024, and then it looks like they pushed it back roughly a half year after tape in.
Who knows maybe Intel 4 is also behind as well, but both rumors, Intel's own announcements, and the timelines seem to indicate it's the design team that screwed up for MTL.

 

[Geddagod]

We're days away from Q2 '24. The earliest we will see Intel 4 appears to be Q4 '24. How is that not behind schedule? And you keep focusing on density as it is the "be all". You even admit OG 10nm was crap. By your logic it should have been awesome because it was supposed to be 2.7x more dense than 14nm.

People, inclusing investors, don't care about density or things like that. They care about performance, margins, etc.

I'm focusing on the density of Intel 4 because that's the point I'm arguing.
@Markfw claimed we know nothing about Intel 4, and I disputed it seeing as we know density. That's literarily all I'm debating.
I don't know why your trying to apply my "logic" to 10nm, since the value of the overall node wasn't ever the point I was arguing anyway.
I understand you not knowing my point, if you just didn't want to read all my messages about it above. In nearly every message, I swear, I included that idk about Intel 4 fMax, or Intel 4 yields, or anything like that, and that Intel 4 could end up being a crappy node. But if you don't want to know about what my point is, fine, but please don't try presuming your own interpretation of it.

 

[nicalandia]

One of SPR's bottlenecks looked to be the L3.
EMR is rumored to massively expand L3 size.
Could actually provide a decent uplift in some workloads.

Highly unlikely that Intel is going from a 1.875 MiB per core of L3 to 5 MiB per core. EMR is just a refresh of SPR built on Intel 7 there is absolutely no chance of such drastic change. EMR was to be easier to deploy due to small amount of validation requiered since its a refresh SPR with max 64 cores and will be socket compatible. There is no way to put x2.66 amount L3 on the same package

 

[Geddagod]

Highly unlikely that Intel is going from a 1.875 MiB per core of L3 to 5 MiB per core.

Mhmm. That's why I was so doubtful too when I discussed about in this forum too.
I'm trying to remember where I heard about it on twitter. WildC? I think?
But based on the chips and cheese article, I think Intel will change something about the L3.
It's a relatively easy change that could cause a potentially marginal performance uplift in some tasks.
Raichu also commented on extra cache in the interconnect for EMR, though he did not include any specific numbers.

 

[Thunder 57]

Again, Intel never claimed Intel 4 would show up in products by Q2 2022. They said HV manufacturing ready, and Intel still claims Intel 4 is HVM ready.
What is also behind schedule is MTL design/execution team. Raichu claims that it was targeted for a 1H 2023 launch, like I think nearly a year ago, if not more.
But even ignoring rumors, you can see the delays in development when you look at when MTL development schedule:

• MTL taped in end of 1H 2021. slightly less than 2 years after should be the release date. 1H 2023.
• MTL powered on 2Q 2022. ~15 months later, we should see release date. 3Q 2023.

So ye, MTL seems to have been pushed back a quarter or so between tape in and power on, but that could also be a margin of error between development of different products. Until you realize that MTL is still likely not going to end up launching until the very end of 2024, and then it looks like they pushed it back roughly a half year after tape in.
Who knows maybe Intel 4 is also behind as well, but both rumors, Intel's own announcements, and the timelines seem to indicate it's the design team that screwed up for MTL.

Why won't we see MTL until later this year? Either MTL was delayed, or Intel 4. Either way, it's not a good look.

I'm focusing on the density of Intel 4 because that's the point I'm arguing.
@Markfw claimed we know nothing about Intel 4, and I disputed it seeing as we know density. That's literarily all I'm debating.
I don't know why your trying to apply my "logic" to 10nm, since the value of the overall node wasn't ever the point I was arguing anyway.
I understand you not knowing my point, if you just didn't want to read all my messages about it above. In nearly every message, I swear, I included that idk about Intel 4 fMax, or Intel 4 yields, or anything like that, and that Intel 4 could end up being a crappy node. But if you don't want to know about what my point is, fine, but please don't try presuming your own interpretation of it.

I don't see why arguing density matters. We should be arguing the quality of a product and its abaility to ship on time. I have as much faith in the roadmap I posted above as this one.

Highly unlikely that Intel is going from a 1.875 MiB per core of L3 to 5 MiB per core.

Even if they could it wouldn't fix the latency.

 

[Geddagod]

Highly unlikely that Intel is going from a 1.875 MiB per core of L3 to 5 MiB per core. EMR is just a refresh of SPR built on Intel 7 there is absolutely no chance of such drastic change. EMR was to be easier to deploy due to small amount of validation requiered since its a refresh SPR with max 64 cores and will be socket compatible. There is no way to put x2.66 amount L3 on the same package

Oop just saw the edit.
Also HXL just recently tweeted this: 64 C with 320MB L3 cache.
Absolutely no chance is a stretch. I think it's possible. I'll try calculating how much it might increase the die size total later, but also adding cache doesn't blow up validation time or anything like that either. It's no where near as hard as validating lets say a new architecture.
Also, we know EMR is going to use a separate die from SPR. EMR is a new tile design from SPR, since SPR at max can only support 60 cores. If Intel 7 yields are good enough, I don't really see why Intel won't add extra cache into EMR, even if it's not as much as 5MB per core.

 

[nicalandia]

Also HXL just recently tweeted this: 64 C with 320MB L3 cache.
Absolutely no chance is a stretch. I think it's possible.

I believe the 320 MiB number is coming from a 2S 168 Core system reading, a 2.5 MiB per core is definitely possible.

 

[Geddagod]

Why won't we see MTL until later this year? Either MTL was delayed, or Intel 4. Either way, it's not a good look.



I don't see why arguing density matters. We should be arguing the quality of a product and its abaility to ship on time. I have as much faith in the roadmap I posted above as this one.



Even if they could it wouldn't fix the latency.

MTL wouldn't be considered officially delayed, since it would still be a 2023 launch. Just won't in 1H 2023 like Intel were apparently planning it to be, but 2H 2023. It's not a good look either way, sure.
Arguing density matters since it's one of the big 3 design parameters - PPA - performance, power, area.
And don't ask me why so many people couldn't believe we have density info on Intel 4 ¯\_(ツ)_/¯
We could also be arguing about products, but nodes are also important too, since you know, products are fabbed on nodes.
I was also trying my hand on analyzing MTL RWC compared to GLC (like semianalysis) as well as see what I could do in comparison to Zen 4 as well. Might do a lil write up too, idk.
Also high L3 latency is pretty much intrinsic to this monolithic design since the entire point is for one core to have access to the entire chip's worth of cache. Add to that, even GLC client on ringbus has higher L3 latency than zen 4 (and zen 3 too I'm pretty sure) anyway.

 

[moinmoin]

I have as much faith in the roadmap I posted above as this one.

wtftech doesn't allow directly linking images, I think you meant this one?

 

[RTX2080]

What will happen? MTL-S and MTL-P seems MIA, and ARL-S get accelerated but I'm afraid it is impossible.

https://twitter.com/x/status/1636684476834258944

Intel's 2024 Arrow Lake-S desktop CPUs to feature up to 24 cores and support DDR5-6400 memory - VideoCardz.com

Intel 14th Gen Core Series rumors Intel is renaming and shifting its next-gen desktop product stack, claims a new rumor from Benchlife. A rumor alleges that Intel might have changed its plans for the Meteor Lake-S CPU architecture. The product which was expected between late 2023 and early 2024...

videocardz.com

There may have been some changes in Intel’s product planning for desktop computers. The previously rumored Meteor Lake-S, which was expected to launch in the first half of 2024, may be renamed Arrow Lake-S and paired with the Intel 800 series chipset. Both Meteor Lake-S and Arrow Lake-S use the Intel LGA 1851 socket. According to the source, Arrow Lake-S will maintain a maximum 8P+16E core configuration, while the 6P+16E configuration for MTL-S will be canceled.

— Benchlife

 

[DrMrLordX]

What was in 2019? Tigerlake or Rocket?

IceLake-U:

Ice Lake U - Cores - Intel - WikiChip

Ice Lake U (ICL-U) is the code name for Intel's line of low-power mobile processors based on the Ice Lake microarchitecture, succeeding Cannon Lake U, Whiskey Lake U, and Coffee Lake U. These chips are primarily targeted towards mainstream through premium tablets, thin-and-light, and other...

en.wikichip.org

TigerLake was 2020, and Rocket Lake was 2021.

Looks like the actual rumor is that Meteorlake is going away and Arrowlake is being pulled forward to Q1 2024. More believeable, but I have little faith in Intel's execution.

That could be quite a disaster. So much for Intel 4. It seems like the only way Intel could pull ArrowLake forward would be to put it on N3. 20a will not be ready in that timeframe - if ever!

 

[uzzi38]

What will happen? MTL-S and MTL-P seems MIA, and ARL-S get accelerated but I'm afraid it is impossible.

https://twitter.com/x/status/1636684476834258944

Intel's 2024 Arrow Lake-S desktop CPUs to feature up to 24 cores and support DDR5-6400 memory - VideoCardz.com

Intel 14th Gen Core Series rumors Intel is renaming and shifting its next-gen desktop product stack, claims a new rumor from Benchlife. A rumor alleges that Intel might have changed its plans for the Meteor Lake-S CPU architecture. The product which was expected between late 2023 and early 2024...

videocardz.com

MTL-S and MTL-P are both still alive and both the same die.

ARL-S is not accelerated. Benchlife misunderstood the roadmap they have access to them.

 

[Hitman928]

Never heard of 10nm+ changing anything.
Here's the quote about 10nm SF from Anandtech's article on it:

So SF actually increased density.
Intel also disclosed transistor counts for SPR, and engineer for SPR said 11 billion transistors IIRC. Idk about alder lake/raptor lake though.

This doesn't read to me that they increased transistor density at all but instead is telling me that they reduced transistor density for 10SF while maintaining or decreasing overall area. The reason less transistors were needed was due to the lower density cells being higher performance and needing less buffering. So you have lower density transistor spacing within the cells and fewer transistors in those cells as well. In other words, you have significantly lower transistor density, but overall area actually decreases due to needing much less transistors.

 

[Markfw]

I'm focusing on the density of Intel 4 because that's the point I'm arguing.
@Markfw claimed we know nothing about Intel 4, and I disputed it seeing as we know density. That's literarily all I'm debating.
I don't know why your trying to apply my "logic" to 10nm, since the value of the overall node wasn't ever the point I was arguing anyway.
I understand you not knowing my point, if you just didn't want to read all my messages about it above. In nearly every message, I swear, I included that idk about Intel 4 fMax, or Intel 4 yields, or anything like that, and that Intel 4 could end up being a crappy node. But if you don't want to know about what my point is, fine, but please don't try presuming your own interpretation of it.

I did NOT say we know nothing about Intel 4. But I DID say that until a real product has rolled off the line and somebody can evaluate it, its still a PLAN and not a reality or FACT. Things could change between expectations and reality, as they have in the past for Intel. It IS a fact that Intel has not met expectations, and its in the quarterly reports by their own admission !!

 

[Geddagod]

I did NOT say we know nothing about Intel 4. But I DID say that until a real product has rolled off the line and somebody can evaluate it, its still a PLAN and not a reality or FACT. Things could change between expectations and reality, as they have in the past for Intel. It IS a fact that Intel has not met expectations, and its in the quarterly reports by their own admission !!

They haven't met their expectations... financially? roadmap wise?
And btw, Intel 10ESF didn't have their products inspected either by any research company like techinsights, afaik. So what, 10ESF just doesn't exist either?
All the info we have on these nodes, are from the companies themselves. There aren't many validators out there. The equipment to properly analyze them is expensive, and all the stuff is paywalled regardless.
Node dimensions didn't change between "expectations and reality" in the past between Intel releasing official information and products rolling out.
Pretending not meeting roadmaps presented in investor meetings and transistor dimension information released in academia are the same thing is disingenuous and just wrong.
We know what Intel 4, the node is. Just because it is not in a product, doesn't mean it doesn't exist lmao. A node, and an actual product, are two separate things.
Besides, even for the product aspect of it, I did a lil mini write up of how it certainly looks like Intel 4 is reaching their promised density claims in RWC regardless.

 

[Geddagod]

This doesn't read to me that they increased transistor density at all but instead is telling me that they reduced transistor density for 10SF while maintaining or decreasing overall area. The reason less transistors were needed was due to the lower density cells being higher performance and needing less buffering. So you have lower density transistor spacing within the cells and fewer transistors in those cells as well. In other words, you have significantly lower transistor density, but overall area actually decreases due to needing much less transistors.

You might be right. I'm going to see if I can find a bit more into it.
Idk about significantly lower transistor density though...
Either way, icelake was still released on 10nm+ and not 10nm SF...
And so the idea that Intel lied about 10nm HD max density is still false, or didn't release products with claimed density (for the HD cells in products atleast), is still false, as 10nm Icelake products still used HD cells in their iGPUs.

 

[Hitman928]

You might be right. I'm going to see if I can find a bit more into it.
Idk about significantly lower transistor density though...
Either way, icelake was still released on 10nm+ and not 10nm SF...
And so the idea that Intel lied about 10nm HD max density is still false, or didn't release products with claimed density (for the HD cells in products atleast), is still false, as 10nm Icelake products still used HD cells in their iGPUs.

We don't know if the HD cells in Ice Lake have the same density as the HD cells in Cannon Lake, I'm guessing not due to Ice Lake still having yield and performance issues which they solved with 10SF by (further?) decreasing density. Intel basically went completely silent on what changes they made to 10nm+ to improve it from the original 10nm. They actually went even further and tried to pretend that the original 10 nm never existed due to how bad it failed as a process. The original 10nm was unworkable and Intel themselves don't want us to consider it as having ever existed, so personally, I don't see how it can be counted as a process that met expectations, even if yields aren't considered (which they must be, a process with horrific yields is meaningless).

Honestly, it doesn't really matter, we'll see how Intel 4/3 turns out soon enough. They've dumped a ton of money into the upcoming nodes to hopefully it goes much smoother but I wouldn't be surprised at all if they have to relax their specs or maybe hit their specs but are hit with delays to the point where they are still behind due to the other 2 players not experiencing such delays. Considering IFS is a big part of Intel's current plan to get back to leadership, I really hope they have things working this time.