Discussion Intel current and future Lakes & Rapids thread

[Hitman928]

You might be right. I'm going to see if I can find a bit more into it.
Idk about significantly lower transistor density though...
Either way, icelake was still released on 10nm+ and not 10nm SF...
And so the idea that Intel lied about 10nm HD max density is still false, or didn't release products with claimed density (for the HD cells in products atleast), is still false, as 10nm Icelake products still used HD cells in their iGPUs.

We don't know if the HD cells in Ice Lake have the same density as the HD cells in Cannon Lake, I'm guessing not due to Ice Lake still having yield and performance issues which they solved with 10SF by (further?) decreasing density. Intel basically went completely silent on what changes they made to 10nm+ to improve it from the original 10nm. They actually went even further and tried to pretend that the original 10 nm never existed due to how bad it failed as a process. The original 10nm was unworkable and Intel themselves don't want us to consider it as having ever existed, so personally, I don't see how it can be counted as a process that met expectations, even if yields aren't considered (which they must be, a process with horrific yields is meaningless).

Honestly, it doesn't really matter, we'll see how Intel 4/3 turns out soon enough. They've dumped a ton of money into the upcoming nodes to hopefully it goes much smoother but I wouldn't be surprised at all if they have to relax their specs or maybe hit their specs but are hit with delays to the point where they are still behind due to the other 2 players not experiencing such delays. Considering IFS is a big part of Intel's current plan to get back to leadership, I really hope they have things working this time.

 

[Markfw]

We don't know if the HD cells in Ice Lake have the same density as the HD cells in Cannon Lake, I'm guessing not due to Ice Lake still having yield and performance issues which they solved with 10SF by (further?) decreasing density. Intel basically went completely silent on what changes they made to 10nm+ to improve it from the original 10nm. They actually went even further and tried to pretend that the original 10 nm never existed due to how bad it failed as a process. The original 10nm was unworkable and Intel themselves don't want us to consider it as having ever existed, so personally, I don't see how it can be counted as a process that met expectations, even if yields aren't considered (which they must be, a process with horrific yields is meaningless).

Honestly, it doesn't really matter, we'll see how Intel 4/3 turns out soon enough. They've dumped a ton of money into the upcoming nodes to hopefully it goes much smoother but I wouldn't be surprised at all if they have to relax their specs or maybe hit their specs but are hit with delays to the point where they are still behind due to the other 2 players not experiencing such delays. Considering IFS is a big part of Intel's current plan to get back to leadership, I really hope they have things working this time.

This is exactly what I have been trying to say to gettagod, but he keeps arguing with me over semantics or something.

 

[Geddagod]

We don't know if the HD cells in Ice Lake have the same density as the HD cells in Cannon Lake, I'm guessing not due to Ice Lake still having yield and performance issues which they solved with 10SF by (further?) decreasing density. Intel basically went completely silent on what changes they made to 10nm+ to improve it from the original 10nm. They actually went even further and tried to pretend that the original 10 nm never existed due to how bad it failed as a process. The original 10nm was unworkable and Intel themselves don't want us to consider it as having ever existed, so personally, I don't see how it can be counted as a process that met expectations, even if yields aren't considered (which they must be, a process with horrific yields is meaningless).

Honestly, it doesn't really matter, we'll see how Intel 4/3 turns out soon enough. They've dumped a ton of money into the upcoming nodes to hopefully it goes much smoother but I wouldn't be surprised at all if they have to relax their specs or maybe hit their specs but are hit with delays to the point where they are still behind due to the other 2 players not experiencing such delays. Considering IFS is a big part of Intel's current plan to get back to leadership, I really hope they have things working this time.

We don't know the density of literarily anything except what Intel says, and the one cannon lake chip.
Intel never claimed they changed transistor density on Intel 10nm+, and yet they were willing to claim it on Intel 10SF, so that point doesn't really make sense.
What Intel might have done to improve yields, and like what they did with ADL-S and RPL-S was implement taller cells in order to increase yield.
However this isn't changing the core tenants of the transistor size, but just using higher performing but less dense cells.

 

[Thunder 57]

This chip performs better, but that one is built on a process that is more dense, so I'll take that one please, said no one ever.

 

[Geddagod]

This chip performs better, but that one is built on a process that is more dense, so I'll take that one please, said no one ever.

What?

 

[Geddagod]

This is exactly what I have been trying to say to gettagod, but he keeps arguing with me over semantics or something.

Lol what semantics?
You quite literarily said we don't know anything about Intel 4, or at least we shouldn't count what we know about about Intel 4, because MTL isn't out yet.
That's just false because as an industry we know dimensions about a node before the product actually releases.
We know the dimensions about TSMC 3nm as well,
And if they do end up changing, the foundries disclose that.
For example, N3 vs N3E, or Intel 10nm vs Intel 10nm SF.

 

[Edrick]

I believe the 320 MiB number is coming from a 2S 168 Core system reading, a 2.5 MiB per core is definitely possible.

2.5MB per core is definitely more realistic than 5MB per core. (I think you meant 2S 128 core system)

 

[Geddagod]

What you, @Markfw, seems to be confused about is this:
You don't need a product to know about the node.
The node is separate from the product itself.
The max theoretical density of a node is never achieved on a product because of different combinations of cells, SRAM, and even stuff like routing.

The problem with saying, "oh Intel 10nm never saw any real volume" is that regardless the claimed density for Intel 10nm did show up in the chip.
And so Intel 4 could also have terrible yields, but the idea that we don't know what density it was because MTL isn't out yet is just wrong.
And this isn't semantics, it was the entire point I was disagreeing with all the way from the start : https://forums.anandtech.com/thread...ure-lakes-rapids-thread.2509080/post-40969579

 

[Hitman928]

We don't know the density of literarily anything except what Intel says, and the one cannon lake chip.
Intel never claimed they changed transistor density on Intel 10nm+, and yet they were willing to claim it on Intel 10SF, so that point doesn't really make sense.
What Intel might have done to improve yields, and like what they did with ADL-S and RPL-S was implement taller cells in order to increase yield.
However this isn't changing the core tenants of the transistor size, but just using higher performing but less dense cells.

They didn't claim any changes about 10nm+ because they literally pretended that 10 nm didn't exist. Obviously they changed something to improve yields. If they decreased density with 10SF to improve yield, it makes perfect sense that they decreased density with 10nm+ to improve yields as well. Do we know this for a fact? No, because again, Intel went completely silent on the matter. Either way, the original 10 nm was by all accounts a failed process and at best, it took them an additional 3 -4 years to get something working at least well enough for a high volume release but even then yields were not great and supply and performance were limited. It took another iteration with decreased density (and other changes) to finally start getting something they could get good yields out of and by the time it came out, TSMC was on 5 with great yields.

The problem with saying, "oh Intel 10nm never saw any real volume" is that regardless the claimed density for Intel 10nm did show up in the chip.
And so Intel 4 could also have terrible yields, but the idea that we don't know what density it was because MTL isn't out yet is just wrong.

The point is that no one will care what the specs of the process are if Intel 4 is a repeat of 10nm. A broken process that tapes out 1 design in a tiny volume to try and appease investors is meaningless. You can argue, but it did exist! Sure, technically it existed, but it had zero impact on anything other than burning through more of Intel's cash and the original process was abandoned. If they have to modify the process and decrease specs in order for it to yield anything, then people will consider the modified specs as the real process because you couldn't actually make anything with the original. Even Intel wants us to think this way about 10 nm. Until Intel can prove that they can actually hit their target specs with workable yields and do so in a time frame where the process is actually competing with TSMC's best, people are going to be extremely skeptical of Intel's claims and want to see actual yielding product before accepting that they accomplished what they said they could.

 

[Geddagod]

They didn't claim any changes about 10nm+ because they literally pretended that 10 nm didn't exist. Obviously they changed something to improve yields. If they decreased density with 10SF to improve yield, it makes perfect sense that they decreased density with 10nm+ to improve yields as well. Do we know this for a fact? No, because again, Intel went completely silent on the matter. Either way, the original 10 nm was by all accounts a failed process and at best, it took them an additional 3 -4 years to get something working at least well enough for a high volume release but even then yields were not great and supply and performance were limited. It took another iteration with decreased density (and other changes) to finally start getting something they could get good yields out of and by the time it came out, TSMC was on 5 with great yields.



The point is that no one will care what the specs of the process are if Intel 4 is a repeat of 10nm. A broken process that tapes out 1 design in a tiny volume to try and appease investors is meaningless. You can argue, but it did exist! Sure, technically it existed, but it had zero impact on anything other than burning through more of Intel's cash and the original process was abandoned. If they have to modify the process and decrease specs in order for it to yield anything, then people will consider the modified specs as the real process because you couldn't actually make anything with the original. Even Intel wants us to think this way about 10 nm. Until Intel can prove that they can actually hit their target specs with workable yields and do so in a time frame where the process is actually competing with TSMC's best, people are going to be extremely skeptical of Intel's claims and want to see actual yielding product before accepting that they accomplished what they said they could.

While they did rebadge 10nm+ as 10nm, that doesn't mean that there were any major rebuilds on 10nm+. You're right, it makes sense that they might have decreased density for icelake, but not transistor density but rather the selection of cells they used in their products. We already know this is what Intel did previously based on Alder Lake, so it makes no sense why they couldn't have done a similar thing for Icelake in some blocks.
Also, if I'm reading Redfire's chart right, Intel made UHP libs for Intel 10nm+ and not Intel 10nm, meaning that they likely used UHP libs in icelake to further decrease density and increase yields, without having to touch the actual size of the transistor.
There are many different ways to increase density regardless without decreasing density as well.
There is literarily no evidence to a decreasing of transistor density on Intel 10nm+.
But even if you ignore Icelake. the idea that Intel 10nm ESF decreased "spec" is still just silly, since overall it's an increase in density regardless of changes done to gate pitch. If that's what ends up happening to Intel 4, I don't think anyone would be disappointed

The entire point of the convo was to show that you don't need a product on the node to know the physical dimensions of a node, not that Intel 4 is going to be a successful node. Which idk why you keep on insisting I am trying to say, when I have reiterated that point that Intel 4 may have terrible clocks of yield bad.
You are trying to argue something which no one is arguing for.

 

[Geddagod]

It would be incredibly, incredibly ironic if Granite Rapids ends up having more cores than Zen 5... the theoretical max barring yields for GNR is apparently 132

 

[igor_kavinski]

It would be incredibly, incredibly ironic if Granite Rapids ends up having more cores than Zen 5

That's still a useless metric to compare them for real world use cases, other than maybe handling high volume transactional processing. Zen 5 with fewer cores might still outrun Granite Rapids in typical workloads.

 

[Hitman928]

But even if you ignore Icelake. the idea that Intel 10nm ESF decreased "spec" is still just silly, since overall it's an increase in density regardless of changes done to gate pitch. If that's what ends up happening to Intel 4, I don't think anyone would be disappointed

It decreased area, not density, there is a difference. Ultimately it's a good move for the end product, but from a process stand point, it's a degradation.

The entire point of the convo was to show that you don't need a product on the node to know the physical dimensions of a node, not that Intel 4 is going to be a successful node. Which idk why you keep on insisting I am trying to say, when I have reiterated that point that Intel 4 may have terrible clocks of yield bad.
You are trying to argue something which no one is arguing for.

Achieving density on a process no one can actually use due to terrible yields is pointless. While technically the node may exist, for practical purposes it's vaporware. I don't know how else to make the point so we'll probably just have to accept that we don't see things the same way.

 

[Geddagod]

That's still a useless metric to compare them for real world use cases, other than maybe handling high volume transactional processing. Zen 5 with fewer cores might still outrun Granite Rapids in typical workloads.

Key word - ironic.
I also think Zen 5 is going to end up having higher IPC. Frequency? Who knows.

 

[Geddagod]

It decreased area, not density, there is a difference. Ultimately it's a good move for the end product, but from a process stand point, it's a degradation.



Achieving density on a process no one can actually use due to terrible yields is pointless. While technically the node may exist, for practical purposes it's vaporware. I don't know how else to make the point so we'll probably just have to accept that we don't see things the same way.

If overall cell size decreases for libs, density would increase.
It's worse on the transistor level, but since libs are still part of the process, it's not a bad trade off for the process as a whole either.
Even if Intel 4 ends up being vapor ware, the fact that we know information about it is still true.
Agree to disagree ig.
¯\_(ツ)_/¯

 

[Geddagod]

Something interesting from Jim's video about Intel is the part about ARL-P being on TSMC 3nm as well.
The latest rumors claim that Intel ARL desktop is on TSMC 3nm, while mobile is on Intel 20A.
But if ARL-P is also on TSMC 3nm, what's going to be fabbed on Intel 20A? And if the P series are on TSMC 3nm, wouldn't the H series also make sense to be on TSMC 3nm?
So that leaves the U series. Ultra thins. It makes sense if Intel 20A is just going to be a very low power focused node without having to deal with the issues of high clocks until later....
Until you remember LNL also exists. And is specifically created for low power usage... and is also supposed to launch in a timeframe not all that different from ARL.
So what the heck, in ARL, is going to be using Intel 20A??

 

[Hitman928]

If overall cell size decreases for libs, density would increase.
It's worse on the transistor level, but since libs are still part of the process, it's not a bad trade off for the process as a whole either.

Yes, cell density would increase but actual transistor density decreases and transistor density is how the processes are judged. But as I said, overall it's the right move for Intel.

Even if Intel 4 ends up being vapor ware, the fact that we know information about it is still true.

If Intel 4 as known today ends up being vaporware and they have to adjust specs down to actually make products on it, then the current comparison between Intel 4 and other processes is meaningless. That's all myself and others have been trying to say. It's all, "paper specs" until Intel can prove that they can actually use the process for volume products. If you don't think a process being able to yield an actual product matters, then yes, we just see things differently.

 

[Geddagod]

Yes, cell density would increase but actual transistor density decreases and transistor density is how the processes are judged. But as I said, overall it's the right move for Intel.



If Intel 4 as known today ends up being vaporware and they have to adjust specs down to actually make products on it, then the current comparison between Intel 4 and other processes is meaningless. That's all myself and others have been trying to say. It's all, "paper specs" until Intel can prove that they can actually use the process for volume products. If you don't think a process being able to yield an actual product matters, then yes, we just see things differently.

They didn't really have to change specs of Intel 10nm to get it to work though. The 10nm+ lowering density of the transistor is speculation at best, and 10nm SF having lower gate pitch, by a margin so small that it allowed less buffers to cause an overall increase in density, didn't change much density either. And even then 10nm SF was released years later. Unless you really think Intel pulled a fast one over essentially all of tech academia as well...
I do think having a process that yields products matters, I don't think you need a product to launch on a node for you to believe the information such as node dimensions.
"Paper specs" are one thing, but claiming the specs just don't exist or aren't true because a product doesn't utilize them is another.

 

[nicalandia]

More Competitive? Measured against what CPU Exactly?

 

[Hitman928]

They didn't really have to change specs of Intel 10nm to get it to work though. The 10nm+ lowering density of the transistor is speculation at best, and 10nm SF having lower gate pitch, by a margin so small that it allowed less buffers to cause an overall increase in density, didn't change much density either. And even then 10nm SF was released years later. Unless you really think Intel pulled a fast one over essentially all of tech academia as well...
I do think having a process that yields products matters, I don't think you need a product to launch on a node for you to believe the information such as node dimensions.
"Paper specs" are one thing, but claiming the specs just don't exist or aren't true because a product doesn't utilize them is another.

Ok, I understand your position, I just don't agree with it but that's ok.

One point though is that you keep saying that 10nm SF density increased, but this is not true from the explanation in the Anandtech article. Density is transistors per area. So density went down, it's just that they could use fewer, higher performing transistors which more than made up for the decreased density to allow for lower area.

 

[cortexa99]

View attachment 78321

More Competitive? Measured against what CPU Exactly?

Original article is from infamous site Mydrivers(something like WCCF), and their source is one of the analyst from Susquehana which upgrade his outlook about Intel

https://www.nasdaq.com/articles/susquehanna-upgrades-intel-intc


but Mydrivers added comments of theirselves like speculating nothing would be delayed(yet) from Intel in the future, and have a positive outlook about SapphireRapids due to Intel's own report.

 

[A///]

More rumors of mtls canceled in favor of a pushed up arrow. 8+16 isn't bad if the p improves each generation in addition to the e. If Intel can figure out how to incorporate smt in the e and avx512 while addressing their power consumption AMD may very well be in trouble a couple generations from now.

it goes without saying even if amd were equal in performance they would have either increased core counts by then which seems to be the zen 5 rumors alongside a redesigned cores chiplet to advocate such a move but they would lose some advantages like avx512 even though average joe shmoe isn't using it.

 

[uzzi38]

More rumors of mtls canceled in favor of a pushed up arrow. 8+16 isn't bad if the p improves each generation in addition to the e. If Intel can figure out how to incorporate smt in the e and avx512 while addressing their power consumption AMD may very well be in trouble a couple generations from now.

it goes without saying even if amd were equal in performance they would have either increased core counts by then which seems to be the zen 5 rumors alongside a redesigned cores chiplet to advocate such a move but they would lose some advantages like avx512 even though average joe shmoe isn't using it.

MTL-S being cancelled isn't happening, nor is ARL-S pushed up. Benchlife just misunderstood the roadmap.

 

[Asterox]

Key word - ironic.
I also think Zen 5 is going to end up having higher IPC. Frequency? Who knows.

That's not crucial, Intel's biggest problem is the again new Desktop cpu socket in 2024. This is already absurd, and in the end Intel will sink the deepest it has ever been.

 

[Exist50]

MTL-S and MTL-P are both still alive and both the same die.

ARL-S is not accelerated. Benchlife misunderstood the roadmap they have access to them.

It sounds like the situation is that the 6+16 die (assuming it ever existed) was canceled, but we'll still get a 6+8 MTL-S aligned with the ARL launch, with both likely being branded as 15th gen.

MTL 6+8 launch with ARL as 15th gen -> "renamed to Arrow Lake"

That's how I'm mentally translating this.