Discussion Intel current and future Lakes & Rapids thread

[Kocicak]

Overclocker got SPR-W up to 1881 W.

So what. If you recalculate this power draw to a silicone area, what watt/cm2 are you getting in this large CPU in comparison to a regular desktop Raptor lake CPU running at 250W, or even more?

 

[Doug S]

We know the dimensions for the cells for Intel 4. Those dimensions aren't "opinion" they are a fact. Intel released info on it.

You mean like how Intel released info on 10nm? The 10nm CPUs Intel shipped did not have the specs Intel originally claimed when they announced the process and released info on it (years before 10nm stuff shipped in quantity)

Intel's track record is not good, they will need to prove themselves before many of us will take their claims at face value like we once did.

 

[Markfw]

You mean like how Intel released info on 10nm? The 10nm CPUs Intel shipped did not have the specs Intel originally claimed when they announced the process and released info on it (years before 10nm stuff shipped in quantity)

Intel's track record is not good, they will need to prove themselves before many of us will take their claims at face value like we once did.

Exactly the point I have been trying to make for like 2-3 pages. Until its LIVE its only a plan or a target. PERIOD

 

[Geddagod]

You mean like how Intel released info on 10nm? The 10nm CPUs Intel shipped did not have the specs Intel originally claimed when they announced the process and released info on it (years before 10nm stuff shipped in quantity)

Intel's track record is not good, they will need to prove themselves before many of us will take their claims at face value like we once did.

They literarily did. Idk what to tell you.
Intel saying they reached 100mm^2 on HD cells on Intel 10nm wasn't fake. They used HD cells in Intel products for their iGPUs except for ADL and RPL-S apparently. Techinsights also recorded that density on cannon lake. I have no idea what you guys are on about.
Your point about shipping is irrelevant. I'm not claiming Intel 4 is going to have amazing yields or hit 7GHz, but we have information on their density.
Just because Intel doesn't want to use HD cells doesn't mean their density claims become magically false either. Intel's track record has nothing to do with this.

 

[moinmoin]

They used HD cells in Intel products for their iGPUs except for ADL and RPL-S apparently. Techinsights also recorded that density on cannon lake.

The same Cannon Lake that shipped only with all of its iGPU disabled to increase yield?

 

[Geddagod]

The same Cannon Lake that shipped only with all of its iGPU disabled to increase yield?

Yields were horrendous. For like the third time, I'm not commenting on Intel 4 yields, or clocks, simply density. I literarily included this in the line directly below it.
It makes sense because HD cells are harder to yield than HP cells anyway. Raja Koduri himself commented that they switched over to taller cells for ADL-S iGPU since it helped yields.
But tbh, I don't mind cherry picking my comments, but at the very least it would be better if you just cut out the part where I said "iGPUs for products except ADL and RPL-S" since Tiger Lake and before also used HD cells.

 

[nicalandia]

Xeon W9 3495X All Core OC 1900 Watts 132,000 Points.

 

[moinmoin]

Yields were horrendous. For like the third time, I'm not commenting on Intel 4 yields, or clocks, simply density. I literarily included this in the line directly below it.
It makes sense because HD cells are harder to yield than HP cells anyway. Raja Koduri himself commented that they switched over to taller cells for ADL-S iGPU since it helped yields.
But tbh, I don't mind cherry picking my comments, but at the very least it would be better if you just cut out the part where I said "iGPUs for products except ADL and RPL-S" since Tiger Lake and before also used HD cells.

I'm not cherry picking, I just found the quoted section of your comment confusing since you wrote in the first sentence that the iGPU used HD cells, and in the second sentence that Techinsights recorded that density on Cannon Lake, where said iGPU was disabled for yield. That's all.

 

[Geddagod]

Hmph. Well, I apologize if it was confusing.
Regardless though, the 10nm example doesn't work since you know, Intel did end up reaching that density.
Conflating node dimensions and roadmaps is just disingenuous.
First it was with not believing the 'max theoretical density' differences between nodes, then it was claiming we know nothing about Intel 4, now it's thinking Intel was secretly lying about 10nm density claims, like idk what to say. These are like actual conspiracy theories lol.

 

[Doug S]

The same Cannon Lake that shipped only with all of its iGPU disabled to increase yield?

Yep! Cannon Lake was a fake launch to meet investor commitments, it would have never seen the light of day had Intel not told investors they would launch 10nm CPUs by Q2 2018 after previous delays. It was a single stripped down model that shipped in minuscule quantities. Anyone using that as "proof" of anything is extremely desperate!

 

[Geddagod]

Yep! Cannon Lake was a fake launch to meet investor commitments, it would have never seen the light of day had Intel not told investors they would launch 10nm CPUs by Q2 2018 after previous delays. It was a single stripped down model that shipped in minuscule quantities. Anyone using that as "proof" of anything is extremely desperate!

Oh ig so tiger lake and icelake just didn't exist as well?
You know, you could bother to read my response to that right below, instead of trying to make an offhand remark of me being incredibly desperate (while ironically posting incorrect information about maximum theoretical density)
Besides, Idk if you are just purposefully ignoring this or something, but cannon lake was an example of 10nm HD reaching density targets. That's all I used cannon lake for, not as a successful launch or anything. So idk why you are trying to make it seem like I am doing that. Yields were bad, yes. But 10nm didn't have any major changes until 10nm ESF, and density actually increased there.

 

[Geddagod]

Also slight sidebar, idk why you do this @Doug S , but like every single time you get directly confronted about a topic you were wrong about, you never respond back specifically, rather just do something very offhand or indirect. Last time for example, you just said "those who might think..." for our density debate.
I don't mind you pinging me dude, even if you do end up being insulting in the tone of your comment. I like debating about technology, I'll overlook the lack of civility or might even respond with a bit of jest

 

[moinmoin]

Hmph. Well, I apologize if it was confusing.

It still is confusing though, maybe you can resolve it? What did Techinsights actually measure if the densest part is the iGPU and that part is disabled on Cannon Lake? Did they seriously measure the density of a part of the chip that's not actually used as you seemed to imply?

 

[nicalandia]

So what. If you recalculate this power draw to a silicone area, what watt/cm2 are you getting in this large CPU in comparison to a regular desktop Raptor lake CPU running at 250W, or even more?

Trying to do that a such high core clocks its not good because power consumption is not linear. But we can be sure that Xeons have worst watt/mm2 due to its high complexity.

But we can do the math just before the power consumption starts to go wild.

Stock Xeon W9 3495X gets 64,000 points at about 420 Watts. Die area is 1600 mm2.

13900k can do 38,000 points at about 280 Watts. Die area of only 260 mm2.

As you can see the Xeons are really not efficient at all in Performance/Power Consumption/Die area

 

[Geddagod]

It still is confusing though, maybe you can resolve it? What did Techinsights actually measure if the densest part is the iGPU and that part is disabled on Cannon Lake? Did they seriously measure the density of a part of the chip that's not actually used as you seemed to imply?

Just because a part is disabled doesn't mean the transistors magically disappear.
Techinsights is pay walled AFAIK, prob because they are a professional company with the tools and equipment to actually analyze the chip better, but if you go look at their blurb they do confirm density of 100mm^2.
Though however I might have misinterpreted it, 100mm^2 could have been the density of the whole chip not just the iGPU. You could do a quick google search to check it out.

 

[Geddagod]

Also anyone know if chips and cheese posted the parameters he used for GLC in simulating cache variants for GLC using champsim?
Idk how to code, but from what I have seen, it looks like you can pretty easily just change the parameters of the code on champsim pretty straight forwardly from github, and if it is a bit confusing I can get a couple of my friends who do know how to code much better than me to help me out.
Just want to mess around a bit with the program, so if anyone knows if Clam posted that info anywhere it would be much appreciated.

 

[moinmoin]

Just because a part is disabled doesn't mean the transistors magically disappear.

It doesn't make them disappear, but I think it's the crux of the whole discussion, Intel appearing to have a rather bad record of both creating such dense transistors and at the same time actually using them. After all if they are subsequently disabled for whatever reasons they are not actually working as intended, are they?

My personal position in all this is that I hope IFS will be more upfront which such data. Intel up to now liked to essentially play design and foundry departments against each other to obfuscate the real source of the issues they kept having. And I hope we can agree that Intel did have issues.

 

[Geddagod]

It doesn't make them disappear, but I think it's the crux of the whole discussion, Intel appearing to have a rather bad record of both creating such dense transistors and at the same time actually using them. After all if they are subsequently disabled for whatever reasons they are not actually working as intended, are they?

My personal position in all this is that I hope IFS will be more upfront which such data. Intel up to now liked to essentially play design and foundry departments against each other to obfuscate the real source of the issues they kept having. And I hope we can agree that Intel did have issues.

I mean Intel was as upfront as they could be with Intel 4 data, such as the V/F curve, some stuff on leakage and stuff, and the dimensions of the node. I understand not believing the whole "Intel 4 is ready to ramp q4 2022" shtick, but the empirical data on the node?
And sure 10nm HD might not have been yielding like intended, or hitting Fmax like intended, but analysis showed, at the very least, it was hitting density as intended. Plus I don't think Intel made any technical claims for stuff like yields or Fmax of Intel 10nm either. They might have shown projected yield which ended up to be wrong, but that would've been disclosed to be projected anyway. Stuff like clock speeds are a direct casualty of stuff like yield as well, but if your yield is terrible, density of each individual cell isn't effected.
There is a point to be made about Intel being bad at using dense nodes first, but the thing is Intel 4 is HP cells only, not HD cells. They aren't even bothering with HD cells until Intel 3. It looks like they learned their lesson with going for density first. Intel 4 cells on their own are very impressive in terms of density, but it's also important to remember these are HP cells, the Intel 4 HD cells in Intel 3 should be way denser anyway (like all HD cells are compared to HP cells).

 

[A///]

What Intel says and what Intel does are two different things. Suggesting Intel's info is rock solid is a bit like having nostra use telekenesis to drive you around in your non smart car.

 

[Kocicak]

Stock Xeon W9 3495X gets 64,000 points at about 420 Watts. Die area is 1600 mm2.

13900k can do 38,000 points at about 280 Watts. Die area of only 260 mm2.

Watts per cm2 are similar in both cases, in fact, the 13900K is pushed even harder, because in that area is also a graphic card.

That 2 kW power draw of the CPU with large surface area is nothing remarkable, the silicone is nowadays scorched this way casually.

Performance per area is not a valid comparison, when the CPUs use different sorts of cores and they have different features on the dies.

 

[DrMrLordX]

Regarding Intel 4: we know some of its characteristics in the lab and in the limited launch of Loihi2 samples that may or may not have gone to a select few by now. What we don't know is if that node will launch in a suitable state for commercial products until it actually happens.

Meteor Lake is very late to market. It's possible (though not inevitable) that we'll see relaxed features on the final product. Compare unviable 10nm in Cannonlake VS. 10nm+ in IceLake.

If we had had this discussion in early 2017 about the feature sizes of 10nm we might be having the same back and forth. History teaches us that the "real" 10nm was 10nm+ in 2019, and that that node had different feature sizes than those boasted by Intel for 10nm prior to the launch of Cannonlake.

Sorry if this is perhaps redundant.

 

[Geddagod]

What Intel says and what Intel does are two different things. Suggesting Intel's info is rock solid is a bit like having nostra use telekenesis to drive you around in your non smart car.

Conflating technical information released at an international academic conference (VLSI) and a planned product roadmap is disingenuous.

 

[Geddagod]

Additionally 10nm and 10nm+ didn't have different node dimensions. No idea where people got that info from, I haven't seen it anywhere atleast.
10nm ESF and 10nm had different dimensions, but density overall increased due to it.

 

[Edrick]

As you can see the Xeons are really not efficient at all in Performance/Power Consumption/Die area

Guess its that time now to just wait for EMR and hope for better efficiency.

 

[Geddagod]

Guess its that time now to just wait for EMR and hope for better efficiency.

One of SPR's bottlenecks looked to be the L3.
EMR is rumored to massively expand L3 size.
Could actually provide a decent uplift in some workloads.