It doesn't make them disappear, but I think it's the crux of the whole discussion, Intel appearing to have a rather bad record of both creating such dense transistors and at the same time actually using them. After all if they are subsequently disabled for whatever reasons they are not actually working as intended, are they?
My personal position in all this is that I hope IFS will be more upfront which such data. Intel up to now liked to essentially play design and foundry departments against each other to obfuscate the real source of the issues they kept having. And I hope we can agree that Intel did have issues.
I mean Intel was as upfront as they could be with Intel 4 data, such as the V/F curve, some stuff on leakage and stuff, and the dimensions of the node. I understand not believing the whole "Intel 4 is ready to ramp q4 2022" shtick, but the empirical data on the node?
And sure 10nm HD might not have been yielding like intended, or hitting Fmax like intended, but analysis showed, at the very least, it was hitting density as intended. Plus I don't
think Intel made any technical claims for stuff like yields or Fmax of Intel 10nm either. They might have shown projected yield which ended up to be wrong, but that would've been disclosed to be projected anyway. Stuff like clock speeds are a direct casualty of stuff like yield as well, but if your yield is terrible, density of each individual cell isn't effected.
There is a point to be made about Intel being bad at using dense nodes first, but the thing is Intel 4 is HP cells only, not HD cells. They aren't even bothering with HD cells until Intel 3. It looks like they learned their lesson with going for density first. Intel 4 cells on their own are very impressive in terms of density, but it's also important to remember these are HP cells, the Intel 4 HD cells in Intel 3 should be way denser anyway (like all HD cells are compared to HP cells).
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