Discussion Intel current and future Lakes & Rapids thread

[dullard]

@dullard Perf/clock increases and process is somewhat connected but not entirely dependent on it.

Refinements are a thing you know?

Forget computers. How do cars improve without things like Moore's Law? What about architecture? Even yourself? Computer chips are unique that they have process gains so we tend to forget that. But gains from refinements always exist.

The architectural improvements can be on top of process gains because things can always be done better.

Also little bit of a site note, but when they say 18%, that's at ISO-power. At ISO-clocks the perf/watt improvements are greater. I'm guessing at 18% iso-power, it's ~30% iso-clocks. So lower power chips will benefit even more.

I understand that and agree with that. I work in development of equipment, I can generate gains in many different methods including process gains, waste reductions, better designs, etc.

My question was not conveyed well. Given that Intel claims 18% performance gains at iso-power, I wanted to know the opinions here as to where those 18% performance gains are going. (or actually, the reverse: what individual gains combine into an 18% performance gain assuming it is ran at iso-power conditions).

 

[nicalandia]

Some Locuza Die Shots and Annotations on Sapphire Rapids

 

[Markfw]

Question on core counts for Sapphire Rapids ... Those pics have 15 cpu tiles. Would each one have 4 cores for 60 total/120 threads ?

 

[jpiniero]

Question on core counts for Sapphire Rapids ... Those pics have 15 cpu tiles. Would each one have 4 cores for 60 total/120 threads ?

Yea but 56 is going to be the max that is sold.

 

[Markfw]

Yea but 56 is going to be the max that is sold.

So 4 tiles of 15 have one core disabled ? Thats just weird.

 

[scannall]

So 4 tiles of 15 have one core disabled ? Thats just weird.

Probably for yields.

 

[nicalandia]

So 4 tiles of 15 have one core disabled ? Thats just weird.

According to sources, it's due to Yields

Intel was Originally Planning a 60-Core Xeon Sapphire Rapids-SP CPU w/ 16-Core Chiplets/Tiles [Rumor] | Hardware Times

It appears that Intel was originally planning 60-core 4th Gen Xeon Sapphire Rapids-SP in order to compete with AMD’s Epyc Milan and Genoa lineups, but unsatisfactory yields forced the chipmaker to reduce the core count to 56. This info was shared by @YuuKi_Ans on Twitter. According to the...

www.hardwaretimes.com

 

[nicalandia]

Also did not see this posted.

Intel "In-Field Scan" Coming With Sapphire Rapids As New Silicon Failure Testing Feature - Phoronix

www.phoronix.com

 

[jpiniero]

So 4 tiles of 15 have one core disabled ? Thats just weird.

Each tile is like 400 mm2.

 

[Markfw]

Each tile is like 400 mm2.

Between that and the "In-Field Scan" post above, doesn't this sound like a disaster waiting to happen ? Or it is already happening ? Ever seen a CPU with a high failure rate, and more expected to die, such that they even have a plan for detecting it after you spent thousands on the server ??

 

[nicalandia]

Each tile is like 400 mm2.

about 400 mm2

 

[nicalandia]

Between that and the "In-Field Scan" post above, doesn't this sound like a disaster waiting to happen ? Or it is already happening ? Ever seen a CPU with a high failure rate, and more expected to die, such that they even have a plan for detecting it after you spent thousands on the server ??

Such are the perils of having to make such a HUGE CPU on such a bad process node. They don't have the luxury of small efficient chiplets that are control by an inexpensive IO die that is build on an old and very efficient node(14/12 nm)

 

[Markfw]

Such are the perils of having to make such a HUGE CPU on such a bad process node. They don't have the luxury of small efficient chiplets that are control by an inexpensive IO die that is build on an old and very efficient node(14/12 nm)

Well, I am glad somebody else said that, as I agree, but some would call me biased if I did.

 

[ashFTW]

Between that and the "In-Field Scan" post above, doesn't this sound like a disaster waiting to happen ? Or it is already happening ? Ever seen a CPU with a high failure rate, and more expected to die, such that they even have a plan for detecting it after you spent thousands on the server ??

ALL chips can and will fail in the field over time with extended use. The in-field-scan feature seems to me more like a RAS feature, to be able to check the health of each core for added peace of mind, and for scheduling maintenance etc. I’m guessing it’s a feature that’s requested by companies like Google running gigantic server farms.

 

[eek2121]

Probably for yields.

Doubt it. There will be chips that have all 60 cores exceeding expectations. Intel would be literally throwing money away by not selling a 60-core count CPU, especially since a 60-core chip would easily beat EPYC Milan, and possibly even Milan-X.

Such are the perils of having to make such a HUGE CPU on such a bad process node. They don't have the luxury of small efficient chiplets that are control by an inexpensive IO die that is build on an old and very efficient node(14/12 nm)

Going to disagree here as well. Yields are "near parity with TSMC 7nm" and the Intel 7 itself isn't terrible. In actuality, if this chip were on TSMC 7nm or 6nm, it would have just as many troubles. The reality here is that Intel should have dumped large, monolithic chips this gen, and they did not. THAT is what is hurting them.

EDIT: The more likely scenario is probably some kind of combination of power draw and rarity yields for a chip that large. Time will tell. If it is solely yields, we'll eventually see a 60 core SKU, whether it is a public one or not. If it is a combination of factors, we will not. Either way, 400mm on a non-EUV process isn't going to be pretty, and Intel's current Golden Cover architecture leaves a lot to be desired.

 

[DrMrLordX]

Between that and the "In-Field Scan" post above, doesn't this sound like a disaster waiting to happen ? Or it is already happening ?

Thanks to delays, Sapphire Rapids is already a disaster.

 

[moinmoin]

To me IFS sounds like a potential counterpart of AMD's SCF (scalable control fabric, part of IF), just that Intel sells it as a feature to customers as well.

Any possibility that Keller was already involved in that aspect, or would that rather be a precursor to what he'd push for?

 

[nicalandia]

Going to disagree here as well. Yields are "near parity with TSMC 7nm" and the Intel 7 itself isn't terrible.

Are you going to tell us with a straight face that a HUGE monolithic SPR Compute Tile that measures 400 mm2 has the same yields than an tiny 80 mm2 chiplet?

 

[coercitiv]

Are you going to tell us with a straight face that ...

Stop putting words into his mouth. You referred to Intel 7 as "such a bad process node" and @eek2121 pointed out that Intel 7 isn't significantly behind TSMC N7 in terms of yields.

If you want to retract your previous claim with respect to Intel 7 yields and focus on inherent low yields of big dies (no mater the node), then please do so, otherwise be prepared to debate ALL your claims, not just the ones that you have proof for.

 

[nicalandia]

Stop putting words into his mouth. You referred to Intel 7 as "such a bad process node" and @eek2121 pointed out that Intel 7 isn't significantly behind TSMC N7 in terms of yields.

If you want to retract your previous claim with respect to Intel 7 yields and focus on inherent low yields of big dies (no mater the node), then please do so, otherwise be prepared to debate ALL your claims, not just the ones that you have proof for.

I agree, no matter what process node was used.. 400 mm2 is such a HUGE die that it will have poor YIELDS... I believe we were pointing to Yields.

 

[JoeRambo]

Again, why don't we leave yields to beancounters. I doubt we will ever see proper data to support comparisons between TSMC and Intel ( or Samsung).
Those comparisons between 80mm^2 and 400mm^2 assume that each defect kills a die completely. When in fact there is both plenty of redundancy built in quite some of larger structures like cache, BPUs, TLBs and many other large prominent structures. There is also plenty of of SKUs from both Intel and AMD with varying core numbers (and cache in case of Intel).

So 400 mm^2 will have yields that will be obviously worse than 80mm^2, but in a world where NV is selling GA102 SKUs with 628mm^2 size manufactured at Samsung I would not rush to call them poor just because the die is large. Only bean counters know those numbers, we can only infer them from indirect sources like quarterly reports and sometimes availability.

 

[dullard]

Are you going to tell us with a straight face that a HUGE monolithic SPR Compute Tile that measures 400 mm2 has the same yields than an tiny 80 mm2 chiplet?

While it is true that you get lower yields with bigger chips, I think that image can be misleading. In your image it shows 109 functional 80 mm^2 chiplets (90.8% yield) vs 15 functional 400 mm^2 chips (57.7% yield). That sounds at first glance like 90.8% yield dominates 57.7% yield. Sure, it is better. But how much better?

In a perfect world, you'd need 5 of those 80 mm^2 chiplets to make one 400 mm^2 chip. So, after harvesting the 109 chiplets, you get 21.8 assembled chips. That assumes you can just cut chips up. You can't. You need extra area for communication lines from chiplet to chiplet. So, you are actually closer to ~20 good assembled chips since you'll need bigger than 80 mm^2 chiplets. The assembly process also has yield issues. For the sake of easy math, lets say 95% of the assemblies worked, then you are at a final yield of ~19 good chips from chiplets vs 15 good chips from a giant monolith. And this also assumes the 400 mm^2 monolith is completely destroyed by a defect and cannot be recovered (so actually there will be more than 15 good monoliths). Note: Take my adjustment numbers with a grain of salt, they are just for argument sakes, not perfect representations of all possible combinations of chiplets.

Lets suppose a wafer costs $15000 after all is said and done. Then you are talking $15000 / ~19 = ~$789 per functioning CPU for the chiplet method vs $15000 / ~15 = $1000 per functioning CPU for the monolith method. That doesn't even include the extra cost of testing, sorting, and assembling chiplets. Sure, it is ~$211 cheaper with chiplets. But if you are selling these for $5,000 a pop, the difference is not that important.

The real profit issue is if your 400 mm^2 monolith design or process sucks and you have to sell it for $3000 instead of $5000. The chiplet vs monolith chip debate is a red herring.

 

[nicalandia]

Lets suppose a wafer costs $15000 after all is said and done. Then you are talking $15000 / ~19 = ~$789 per functioning CPU for the chiplet method vs $15000 / ~15 = $1000 per functioning CPU for the monolith method. That doesn't even include the extra cost of testing, sorting, and assembling chiplets. Sure, it is ~$211 cheaper with chiplets. But if you are selling these for $5,000 a pop, the difference is not that important.

Your Napkin math is not adding up..

AMD's chiplet design affords massive cost-cutting opportunities

As TechPowerUp highlights, by limiting the components made on 7nm to those that would tangibly benefit from the cutting-edge fabrication process (the CPU cores) while leaving other...

www.techspot.com

 

[dullard]

Your Napkin math is not adding up..

That just means there are more defects than your first image. Probably because 400 mm^2 is pretty far away from 777 mm^2.

 

[nicalandia]

That just means there are more defects than your first image. Probably because 400 mm^2 is pretty far away from 777 mm^2.

Ture, that was an old 14nm 32 Core... and that Diagram I got it from the Internet it's not mine, but it makes a very good point about the defect rate of large vs small chips