Lets try hypothetical numbers. I'll use 1 core to make it as easy as can be.
- Suppose a hypothetical core calculates 1 billion instructions in 1 second at 1 GHz clock speed using 1 W of power. The IPC is (1 billion instructions) / (1 s) / (1 billion cycles / s) = 1 instruction / cycle.
- Suppose performance / Watt increases 10%.
Now, you have several options, some of which include lowering the power. But in general, OEM builders like a set power limit so they don't have to completely redesign everything from the ground up. I said above that I assume the power is the same. Then since performance/Watt increased 10%, the chip is now performing 1.1 billion instructions in 1 s. There are various ways that this could be accomplished:
1A) That increase could come from IPC gains keeping the clock speed the same. It could now have an IPC of 1.1 instructions / cycle but keep clock speeds the same. Thus in 1 second and at 1 W, it calculates (1.1 instructions / cycle) * (1 s) * (1 billion cycles / second) = 1.1 billion instructions.
1B) That increase could come from clock gains keeping the IPC the same. It could now have a clock rate of 1.1 GHz but keep IPC the same. Thus in 1 second and at 1 W, it calculates (1 instructions / cycle) * (1 s) * (1.1 billion cycles / second) = 1.1 billion instructions.
1C) It could be some combination in between. It could now have an IPC of 1.05 instructions / cycle and a clock rate of 1.0476 GHz. Thus in 1 second and at 1 W, it calculates (1.05 instructions / cycle) * (1 s) * (1.0476 billion cycles / second) = 1.1 billion instructions.
As you see, if the wattage is fixed, then IPC and clock speeds are directly linked.
Yes, there are other options, like lowering thermal design powers. But, that is a fundamental change that I was hoping you'd have explanations for if you think that clock speeds won't change and IPC changes minimally.