Yeah, it definitely feels like something to do with providing the GPU tile with more memory bandwidth. Maybe they'll try to bolt on a GDDR6 interface. Well, something else to ponder I suppose.
It seems Intel really loves high frequencies, and doesn't higher frequencies make chasing IPC gains more difficult? If your target clock speed is 5ghz, it's probably going to be harder to hit a certain IPC gain compared to if the clock speed was 3.5ghz. That said, high frequencies seems to make IPC gains more potent and vice versa as they go hand in hand.
Yes, that's exactly the problem, as I see it. It would have been ok, perhaps, if Arrow Lake were a 2023 product, but 2024? Not good enough.
I've said it before, but I'm increasingly convinced that Arrow Lake and Lunar Lake are much more like contemporaries than successive generations. Good odds they both get branded as 15th gen.
Really don't think they're using Battlemage/Elasti IP for MTL. All the rumors/leaks say 12.7, and their GPU team doesn't seem to be on a yearly cadence. Plus, more churn is the last thing MTL needs.
See, I interpreted 10-12% as the gain from Lion Cove, which is why I'm concerned. I'm hoping that number is iso-power, iso-process or something, and thus we can expect somewhat higher IPC gains, but I'm a poor optimist.
It's not been enough time. Gelsinger can't fundamentally change the pieces Intel has to work with through '23, and likely '24 as well. At best, he can change what's done with those pieces in '24, and stop further bleeding/execution failures, but it'll be years yet before we can see an inflection from him.
When Royal comes out, thank Jim Keller and the team. No one else deserves it.
Intel has used ADM in their Optane memory documents as App Direct Mode, basically letting the specifically written software directly access the Optane data as a form of cache. But, that seems odd for integrated graphics. So, I don't really think they mean App Direct Mode. I'm just tossing that out as a wildcard entry.
Intel has repeatedly stated (including recently in new slides at their Investor Day) that Intel 4 has a ~20% improvement in performance per watt, Intel 3 will be another 18% improvement, and Intel 20A will be another 15%. Now, I realize that you are talking about IPC not performance per watt. But, what gives you confidence that the actual results will be that much lower? Since we can safely assume the wattage limits won't drastically change, the difference between IPC and performance per watt is simply clock speed.
Don't know where you got the info that it's like a cache. App Direct means it can use Optane in native 256 byte access mode, rather than having to translate that to 4KB block mode, so you get the advantages of near DRAM like read latency and persistence.
Yes, but the CEO is the enabler. They'd be looking at worse now if Kraznich was still CEO.
If they hold frequency roughly constant, then the improvements that process delivers (which aren't much these days, but better than nothing) can be devoted to increasing IPC. Sure, if you get a 10% process bump and use it to go from 5 GHz to 5.5 GHz you won't see any IPC benefit, but Intel has basically been stuck at 5 GHz ish for the top end for many years. Not because they couldn't have gone to 6 GHz if they want, but presumably their modeling showed that overall performance (across all dimensions) is worse at that speed by whatever evaluation they use (i.e. however they weight raw performance vs performance per watt vs life expectancy of the chip, etc.)
Wait, what? Process perf/watt improvement is completely orthogonal to IPC. And the reason I'm focusing on IPC (or architecture in general) is that the competition can be presumed to be on an at least equivalent node for the foreseeable future. At least through 2024. That said, I haven't mentioned any intrinsic changes to frequency or power consumption that come with the architecture, but those matter too.
I guess, but in this case it seems more like him continuing something that started before he got there. I suppose that's worth something, but if we're going to give Gelsinger credit, it should be for things that he initiated and supported. Just my two cents.
Not quite. If you have more performance / watt, you can (A) increase clocks, (B) reduce power, (C) increase IPC, or (D) leave it on the table. Option (B) is not likely, power limits don't move that much from generation to generation. Option (D) is unlikely as Intel has been pushing every corner of performance regardless of the potential costs (such as pushing performance past what many of us would call the optimum for power usage). So you are left with increasing clocks or increasing IPC. Your numbers for increasing IPC therefore imply clock frequencies. I just want to know how you are getting your IPC estimates because that ties into what clocks can be utilized.
You can increase IPC without a change in process at all, and by the same token, you can do a node shrink without changing IPC. By no twist of logic can you claim that "the difference between IPC and performance per watt is simply clock speed".
My point was that getting good performance out of high frequency CPUs necessitates other changes, like increasing bandwidth at the cache and system memory level, and lowering latency as much as possible. When I read the Chips and Cheese article for their Golden Cove deep dive, one of the recurrent themes was that Golden Cove is a bandwidth monster, but that seems to come at the cost of latency to some degree, which Intel tries to hide by utilizing various methods. I suppose the Intel architects thought that increasing bandwidth was more important for overall performance than latency?
I agree 100%, but that has absolutely nothing to do with what I was talking about. I must not be writing in a way that conveys my message.
Let me put it another way. Where is Intel putting the extra performance per Watt?
Same as any other node shrink. Less power consumption at low to moderate loads, more performance at high loads. Maybe we can even hope they start getting boost power a little more under control.
And how do they get more performance at high loads? Remember: you said IPC gains will be minimal and you said this has nothing to do with clock speeds.
I said that IPC has nothing to do with clock speed, but for that matter, the perf/watt figure does not directly translate to peak performance either.
So Intel will not be getting "more performance at high loads"?
Going back to the original comment, you were asking me why I expected IPC increases to be small despite the node improvements, right? Well I've answered that, no? I see no inherent connection between IPC and process shrinks, and think they'll just use the gains to more or less implement existing architectures better.
No, you haven't answered it in the slightest. What does "implement existing architectures better" mean? The inherent connection is that clock speeds are allowed to change.
Yes. Changes in clock speed and power at a given speed. Not IPC. Does that clarify?
Lets try hypothetical numbers. I'll use 1 core to make it as easy as can be.
I think I might understand the confusion here. Take that 18% number for Intel 3. That's referring to intrinsic gain from the process, not from subsequent architectures that happen to use it. So architectural changes build on top of that number, not constitute it.
I understand that and agree with that. I work in development of equipment, I can generate gains in many different methods including process gains, waste reductions, better designs, etc.
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