Discussion Intel current and future Lakes & Rapids thread

[nicalandia]

That just means there are more defects than your first image. Probably because 400 mm^2 is pretty far away from 777 mm^2.

Ture, that was an old 14nm 32 Core... and that Diagram I got it from the Internet it's not mine, but it makes a very good point about the defect rate of large vs small chips

 

[dullard]

Ture, that was an old 14nm 32 Core... and that Diagram I got it from the Internet it's not mine, but it makes a very good point about the defect rate of large vs small chips

It does make a good point. I just have seen people take images like that and claim that you get 7x more chips per wafer. You do get more chips per wafer, but it is much closer to 20% to 50% more final CPUs. I wanted to put that all into perspective for those who don't take the time.

 

[nicalandia]

Can someone more adept at this do the math for us? Die size 400 mm2 and input this on this calculator

How big of a Wafer does Intel Uses for their Sapphire Rapids? 16 or 18 Inches?

CALY Technologies

caly-technologies.com

 

[BorisTheBlade82]

Can someone more adept at this do the math for us? Die size 400 mm2 and input this on this calculator

How big of a Wafer does Intel Uses for their Sapphire Rapids? 16 or 18 Inches?

CALY Technologies

caly-technologies.com

View attachment 58209

I'd say 300mm is pretty much the standard.

 

[nicalandia]

I'd say 300mm is pretty much the standard.

Then this is it.

 

[Hitman928]

Then this is it.

View attachment 58210

Scribe lanes are probably bigger than what Intel is using and we don't know their actual density defect rate, but this should be a decent ballpark number.

 

[nicalandia]

I'd say 300mm is pretty much the standard.

You know what? I've been reading and we have been stuck on 300mm for such a long time and the transition to 450 mm has not taken place....

1999
Intel Activates Its 300 Millimeter Wafer Program in

Intel Activates Its 300 Millimeter Wafer Program

2012
Why is 450-mm development so important to Intel (and Samsung and TSMC)?

Why 450mm wafers?

As lithography costs go up, the benefits of a larger wafer size go down. Will the benefits of 450-mm wafers be worth the investment if they only result in a 10% cost reduction per chip?

semiengineering.com

 

[nicalandia]

In a perfect world, you'd need 5 of those 80 mm^2 chiplets to make one 400 mm^2 chip. So, after harvesting the 109 chiplets, you get 21.8 assembled chips.

Can you do your math again with this info?

AMD Zen2 CCD = 92.3% Yield
Intel Sapphire Rapids Compute Tile SOC : 67.9% Yield

 

[dullard]

Can you do your math again with this info?

Chiplet:
(689 functional chiplets / wafer) * (1 CPU / 5 chiplets) = 137.8 CPUs/wafer assuming perfect assembly yield. Round down to 135 just to accept some assembly losses. ($15,000 / wafer) / (135 CPUs / wafer) = $111.11 / CPU. Although, I think you should do it with 88 mm^2 chiplets instead due to some area wasted when you use chiplets.

Monolith:
($15,000 / wafer) / (93 CPUs / wafer) = $161.18 / CPU

That $50/CPU price difference is massive if you are selling $200 desktop chips. It is probably the difference between a big profit and breaking even. $50 is barely noticeable if you are selling $5,000 server CPUs. More important is the total chips you can make. If you are production capped (meaning you can't produce any more than you already are) then lower yields mean you can't sell as many server CPUs, then your loss is way more than the minimal difference in chip production costs. If the market wants thousands of them, and you can only make 93 at a time, then you aren't fulfilling your profit potential. But if you can manufacture 135 in the same time period, then your profit potential skyrockets.

If anyone knows assembled wafer prices better, then I'd be glad to update this post.

 

[nicalandia]

Chiplet:
(689 functional chiplets / wafer) * (1 CPU / 5 chiplets)

Monolith:
($15,000 / wafer) / (93 CPUs / wafer) = $161.18 / CPU



If anyone knows assembled wafer prices better, then I'd be glad to update this post.

Can you clarify this a bit? AMD needs a few chiplets to make a CPU(8 CCD for 64C/128T CPU), But Intel needs 4 Tiles for a single Sapphire Rapids CPU(56C/112T)

So $645 for a 56C/112T Sapphire Rapids CPU and about $180 for a 64C/128T Epyc

 

[dullard]

Can you clarify this a bit? AMD needs a few chiplets to make a CPU(8 CCD for 64C/128T CPU), But Intel needs 4 Tiles for a single Sapphire Rapids CPU(56C/112T)

I'm just doing the very simple and crude back-of-the-envelope calculations. I went with the assumption that you need 400 mm^2 of die space to make a given chip. You could break that up into many different numbers of chiplets. I just assumed you wanted to make that with 5 chiplets of 80 mm^2 each.

Now, if you want to compare one chip from one manufacturer to a completely different sized chip from another manufacturer, go ahead. I try to stay clear from AMD/Intel comparisons as I think they both make great chips.

 

[Saylick]

I don't know if y'all mentioned it earlier, but besides the uptick in yields, a chiplet approach gives you a boost to binning that you wouldn't get with a large monolithic design, i.e. you test each chiplet and only combine the ones that have the best clocks to make your high clocking SKUs vs. monolithic approach where the clocks for the entire die are limited by the slowest core. You might save $50 with chiplets from the cost of materials but you also gain on additional revenue by not having to gimp your best silicon, and thus sell it for less, because a small portion of the die held back the rest.

In other words, there's yield from the stand point of "how many usable dies do I get from my wafer" and then there's yield from the stand point of "how much revenue can I extract from my wafer?". Using a wafer calculator only tells the former. You'd have to be an employee of AMD or Intel to know the latter.

 

[Hitman928]

Chiplet:
(689 functional chiplets / wafer) * (1 CPU / 5 chiplets) = 137.8 CPUs/wafer assuming perfect assembly yield. Round down to 135 just to accept some assembly losses. ($15,000 / wafer) / (135 CPUs / wafer) = $111.11 / CPU. Although, I think you should do it with 88 mm^2 chiplets instead due to some area wasted when you use chiplets.

Monolith:
($15,000 / wafer) / (93 CPUs / wafer) = $161.18 / CPU

That $50/CPU price difference is massive if you are selling $200 desktop chips. It is probably the difference between a big profit and breaking even. $50 is barely noticeable if you are selling $5,000 server CPUs. More important is the total chips you can make. If you are production capped (meaning you can't produce any more than you already are) then lower yields mean you can't sell as many server CPUs, then your loss is way more than the minimal difference in chip production costs. If the market wants thousands of them, and you can only make 93 at a time, then you aren't fulfilling your profit potential. But if you can manufacture 135 in the same time period, then your profit potential skyrockets.

If anyone knows assembled wafer prices better, then I'd be glad to update this post.

A truly monolithic die to match a 5 chiplet CPU would be more on the range of 700mm^2 or more. and you're looking at mid to maybe upper 30s of good dice per wafer for a monolithic solution.

Edit: Sorry, in my head I was thinking different numbers. Comparing a chiplet solution to get to ~64 cores, and taking a ccd of 80 mm^2 with 8 cores per CCD, you would need 700mm^2+ to match in a monolithic die. Of course, you would also need a large IOD for the chiplet solution, around the size of 400mm^2 or so based upon AMD's numbers. Of course, you can put that on an older node to help save on costs as well.

Edit2: My rough math comes out to around 85 fully enabled dies per 2 wafers for chiplet solutions versus 70 fully enabled dies per 2 wafers for monolithic. That makes it $353 per CPU for chiplet and $428.50 for monolithic. If you put the IOD on an older node, I get roughly $273.50 for chiplets (using $15,000/wafer on new node and $8250/wafer on older node). This makes the chiplet approach ~60% of the fabrication cost compared to monolithic which I think is similar to AMD's proclaimed number.

 

[DrMrLordX]

Again, why don't we leave yields to beancounters.

Are we talking 70% vs 90% yields, or 40% vs 60% yields, or what? Below a certain point, it's no longer possible to meet market needs with the product. See: Cannonlake. IceLake-SP was heavily delayed (allegedly due to process yield problems), and now we're seeing similar delays with Sapphire Rapids. Not to ignore 10nm+'s other problems. But 10SF and 10ESF/Intel 7 have the curious issue of having not (yet) been used to bring large dice to the market. Intel never bothered with anything larger than 8c Tiger Lake on 10SF (which in-and-of-itself was relatively late to market vs. 4c Tiger Lake), while 10ESF has never been used for anything larger than the 12900k. Curiously Intel has no present or future plans to attempt more than 8 Golden Cove/Raptor Cove cores on a single die or package on 10ESF.

Are ODMs getting massive shipements of Sapphire Rapids that we don't know about yet? That's not how it was with IceLake-SP, and it appears that Sapphire Rapids will follow the same pattern.

I doubt we will ever see proper data to support comparisons between TSMC and Intel ( or Samsung).

True! We can only infer what we may from end products, and that is imperfect information. But N7 has been used for relatively large dice like . . . I dunno, how about Navi21 with a die size of ~520mm2? Granted those are GPUs so not exactly apples to apples. Note that Intel isn't fabbing any of their GPUs on 10ESF either . . .

We have all these reports now about Sapphire Rapids containing silicon-level redundancy to resist defects, features to permit the CPU to function properly even in the event that some elements of the die are defective, etc. You don't include elements into your design like that if you're expecting high yields.

 

[Doug S]

Probably for yields.

Apple is doing 400+ mm^2 dies for M1 Max and they're selling plenty of units with all cores enabled. Are Intel's yields really so bad that their top SKU is minus one core? I guess chiplets can't come fast enough for them if that's the case.

 

[Hitman928]

To follow up on SPR approach, if wafer cost and yield are the same, you are looking at $645 per CPU for fabrication costs. Now, GC is a comparatively large core compared to Zen3, so if you could decrease core size and you aren't limited by the EMIB/PHY and could get each tile down to, maybe 300mm^2, you are looking at $431.50 per CPU.

 

[jpiniero]

Apple is doing 400+ mm^2 dies for M1 Max and they're selling plenty of units with all cores enabled. Are Intel's yields really so bad that their top SKU is minus one core?

Yes

 

[nicalandia]

To follow up on SPR approach, if wafer cost and yield are the same, you are looking at $645 per CPU for fabrication costs. Now, GC is a comparatively large core compared to Zen3

Xeon based Golden Cove is even larger than the desktop counterpart due to AMX and additional FMA on Port 5

 

[Saylick]

Xeon based Golden Cove is even larger than the desktop counterpart due to AMX and additional FMA on Port 5

View attachment 58213

This really does highlight why Gracemont is so much smaller in die size: it has far less FP capability than Golden Cove due to the lack of FP-dedicated silicon.

 

[ashFTW]

Apple is doing 400+ mm^2 dies for M1 Max and they're selling plenty of units with all cores enabled. Are Intel's yields really so bad that their top SKU is minus one core? I guess chiplets can't come fast enough for them if that's the case.

Apple is binning the M1 Max for the number of GPU cores - 24 or 32. So there are seem to be plenty of non fully functional die. In SPR case 4 die are needed, so 1 defective or deactivated core per die is not a big concern.

If Apple was making 4 time more die with 32 GPU cores vs 24, only then could one claim higher yields.

 

[nicalandia]

This really does highlight why Gracemont is so much smaller in die size.

That is really not a bad thing, Intel could fit 60 Gracemont Cores in a single 400 mm^2 tile for a total of 240 Cores on 4 tiles.

That is what Sierra Forest is going to be Pure Computational Power, Performance/Area

Intel Sierra Forest the E-Core Xeon Intel Needs

We discuss the Intel Sierra Forest announcement at Intel Investor Meeting 2022. This is the high E-core count chip Intel needs

www.servethehome.com

 

[Doug S]

Apple is binning the M1 Max for the number of GPU cores - 24 or 32. So there are seem to be plenty of non fully functional die. In SPR case 4 die are needed, so 1 defective or deactivated core per die is not a big concern.

If Apple was making 4 time more die with 32 GPU cores vs 24, only then could one claim higher yields.

But they are selling plenty that have all GPU and all CPU cores running. Intel isn't. So TSMC must be getting better yields than Intel.

 

[ashFTW]

But they are selling plenty that have all GPU and all CPU cores running. Intel isn't. So TSMC must be getting better yields than Intel.

Do you have data showing how many M1 MAX they are selling with 24 GPU vs 32? Did you see my “SPR needing 4 die“ argument?

 

[JoeRambo]

Intel never bothered with anything larger than 8c Tiger Lake on 10SF (which in-and-of-itself was relatively late to market vs. 4c Tiger Lake), while 10ESF has never been used for anything larger than the 12900k

The thing is, that 12900K is already quite large die, and there is plenty of supply of them. In Skylake era we had quad core desktop 122mm^2 die and XCC was almost 700mm^2.
That's why i doubt they somehow can get 12900K @ 200+ out and have trouble yielding 400mm^2 dies? If anything they are allowing 1 full defective core and chip is loaded with more cache that is easier to make redundant.

We have all these reports now about Sapphire Rapids containing silicon-level redundancy to resist defects, features to permit the CPU to function properly even in the event that some elements of the die are defective, etc. You don't include elements into your design like that if you're expecting high yields.

I think everyone with a clue designs their CPUs with silicon-level redundancy. How else AMD would offer only full L3 chips unless they are either stupid to throw defective ones or yields are incredible from day1. And given Intel's experience with 10nm, they would be stupid to not overengineer in this department. But given that i am typing this on 12900K, the 10ESF must be perfectly fine.
And myself i welcome more RAS features and esp ones that are exposed by Linux kernel. Being able to run low level checks on chip to know it is still sound is a great.

 

[Mopetar]

Apple is doing 400+ mm^2 dies for M1 Max and they're selling plenty of units with all cores enabled. Are Intel's yields really so bad that their top SKU is minus one core? I guess chiplets can't come fast enough for them if that's the case.

But they are selling plenty that have all GPU and all CPU cores running. Intel isn't. So TSMC must be getting better yields than Intel.

We don't know what Apple is getting for yield because we don't see the full product stack yet. I wouldn't be surprised if we see desktop models using their new M1 chips with some disabled CPU cores.

Although the CPU cores are a small part of the silicon and less likely than the GPU to need to be disabled due to being completely nonfunctional, they will still see some or just have others that don't hit performance targets across all cores that need to have some of those cores disabled. There's already a 6-core M1X Pro. I'm not sure if they'll have any 6-core M1X Max parts, but it seems less likely that they'd want to waste the silicon.