Discussion Intel current and future Lakes & Rapids thread

[JoeRambo]

Compared to what? A Vermeer chiplet? Yes. An M1 Max (24c iGPU or otherwise) or Navi21? No.

I already gave that answer:

The thing is, that 12900K is already quite large die, and there is plenty of supply of them. In Skylake era we had quad core desktop 122mm^2 die and XCC was almost 700mm^2.

If there is no shortage of those 8C+8E Cpus, obviuosly they are not having yield problems with 215mm^2 dies. We can conclude that less than 2x larger die is not going to have way worse yield. In Skylake days the difference was not <2x, but 6x instead.

 

[jpiniero]

If there is no shortage of those 8C+8E Cpus, obviuosly they are not having yield problems with 215mm^2 dies. We can conclude that less than 2x larger die is not going to have way worse yield. In Skylake days the difference was not <2x, but 6x instead.

I have to think DIY demand in general is not that great right now because of the GPU shortage... and the market is pretty much buying Ryzen. Meeting demand when there's not much of it isn't a problem.

It took them until Q4 to really launch Icelake Server because of yields and with Sapphire you are talking about 4 for the price of 1.

 

[JoeRambo]

Not sure of Icelake Server has anything to do with current situation and current process health. We have had Tiger Lake and Alder Lake since released in obviously huge numbers.
Just because CannonLake was horrible, does not mean Alder Lake cannot yield?

And that whole "4 for the price of 1" => prices are set by market situation, if that situation erodes AMD/Intel margins, that's even better for us, customers.

 

[jpiniero]

And that whole "4 for the price of 1"

I mean you need 4 working tiles for Sapphire for one chip.

 

[JoeRambo]

It sure is a lot of cutting edge silicon, but i was commenting to "doom up us in department of yields" type of comments earlier. I think the only thing that is not "optimal" for Intel is that they don't have desktop and HEDT market to dump bad tiles ( read with actual defects and ones with bad parametric bins). That's huge advantage to AMD that can continue to pump out a single chiplet and use it everywhere.

 

[jpiniero]

Also remember that Intel made mirrored dies too. So you need 2 of each, and most/all of the IO/EMIB can't have any defects. You probably need most of the cores intact for it to make sense as a product to buy.

I wonder how resilient the EMIB is.

 

[nicalandia]

Also remember that Intel made mirrored dies too. So you need 2 of each, and most/all of the IO/EMIB can't have any defects. You probably need most of the cores intact for it to make sense as a product to buy.

I wonder how resilient the EMIB is.

Correct, this increases complexities and overall price. One Wafer is taped/masked for on side of the mirrored tiles and another Wafer is used for the other side.

 

[Doug S]

Do you have data showing how many M1 MAX they are selling with 24 GPU vs 32? Did you see my “SPR needing 4 die“ argument?

Obviously no one knows that information aside from Apple, but that's irrelevant. They exist, you CAN buy models that don't have any cores disabled. In Intel's case you CANNOT buy anything with SPR that doesn't have cores disabled.

If their yields were sufficient, don't you think they would have a 64 core SPR offering instead of maxing out at 60?

 

[jpiniero]

Come to think of it, Intel should have made a single tile Sapphire work with LGA 1700. Even if it was Xeon E/W only.

 

[DrMrLordX]

I already gave that answer:



If there is no shortage of those 8C+8E Cpus, obviuosly they are not having yield problems with 215mm^2 dies. We can conclude that less than 2x larger die is not going to have way worse yield. In Skylake days the difference was not <2x, but 6x instead.

219mm2 isn't that big compared to the HCC and XCC dice Intel regularly cranked out on even the earliest versions of 14nm. Those went up to ~456mm2! Even the LCC dice were larger than a 12900k.

 

[Saylick]

219mm2 isn't that big compared to the HCC and XCC dice Intel regularly cranked out on even the earliest versions of 14nm. Those went up to ~456mm2! Even the LCC dice were larger than a 12900k.

Yeah, 219 mm2 really isn't that big and definitely not from a historical perspective either. I'd say that Intel 7 is pretty mature at this point. Not sure what the defect rate is compared to TSMC N7 but it's got to be close.

 

[jpiniero]

Yeah, 219 mm2 really isn't that big and definitely not from a historical perspective either. I'd say that Intel 7 is pretty mature at this point. Not sure what the defect rate is compared to TSMC N7 but it's got to be close.

But desktop volume is much lower now and DIY is only a small portion of the market. Not really a valid comparison. Plus they are cutting much more on the products that sell (ie: the i5)

 

[JoeRambo]

It's not like laptop/mobile chips are 50mm^2 either, those are sizeable dies.

But my main point was: the ratio of desktop die to XCC die in Skylake day was almost 6 ( SIX ). And the ratio between ADL-S and Saphire Lake tile is less than 2 ( TWO ).
So server die is not really that big of a step up compared to what it was in Skylake days. And since obviously Intel can produce ADL-S in large numbers and there is no shortage of any SKU, they can yield server tiles as well.

Those are common sense stuff, as only bean counters will have insight and numbers on actual yields and probably no one has numbers to compare between Intel and AMD.

 

[IntelUser2000]

@Doug S Sapphire Rapids tile has a total of 15 cores on die, so the maximum you can get is 60, not 64. With one disabled you get 56.

@jpiniero It's not much lower. And majority of the volume is in the cheap 100mm2 dies. The smallest Alderlake 2+8+2 die is way over that and close to 140mm2 of Tigerlake.

Problems aren't all about yields on the process side. That is long gone now and Intel 7 can be considered mature. Exist50 was talking about design issues with Sapphire Rapids.

219mm2 isn't that big compared to the HCC and XCC dice Intel regularly cranked out on even the earliest versions of 14nm. Those went up to ~456mm2! Even the LCC dice were larger than a 12900k.

It's flavor of the day to fault everything on the process side, but that's likely misguided.

They make only few dies now. Haswell had, many, many different dies. To recount.

4+3 6MB L3
4+2 8MB L3
4+1 6MB L3
2+3 4MB L3
2+3 3MB L3
2+2 4MB L3
2+2 3MB L3
2+1 3MB L3

Intel had EIGHT different dies for regular non-HEDT Haswell. Alderlake has what, 4? In fact the yields will need to be higher not lower, cause the 130-140mm2 smallest die means they need to pump out 50%+ more wafers as they did in the Skylake generation.

 

[jpiniero]

Problems aren't all about yields on the process side. That is long gone now and Intel 7 can be considered mature. Exist50 was talking about design issues with Sapphire Rapids.

I am assuming that Icelake Server's delays (as well as Sapphire's) are due to yields for something that big. They may have put both back in the oven to try to increase redundancy.

 

[IntelUser2000]

I am assuming that Icelake Server's delays (as well as Sapphire's) are due to yields for something that big. They may have put both back in the oven to try to increase redundancy.

Icelake server yes, but not for Sapphire.

 

[Exist50]

Icelake server yes, but not for Sapphire.

Both can blame design for a good chunk. SPR just has less of an excuse from the process side.

 

[repoman27]

They make only few dies now. Haswell had, many, many different dies. To recount.

4+3 6MB L3
4+2 8MB L3
4+1 6MB L3
2+3 4MB L3
2+3 3MB L3
2+2 4MB L3
2+2 3MB L3
2+1 3MB L3

Intel had EIGHT different dies for regular non-HEDT Haswell. Alderlake has what, 4? In fact the yields will need to be higher not lower, cause the 130-140mm2 smallest die means they need to pump out 50%+ more wafers as they did in the Skylake generation.

Don't confuse Intel's myriad of SKUs and market segmentation strategies with actual dies. I only count 3 client dies for Haswell, although one of them did have two steppings:

4+3e HP H/R Model 70 Stepping 1 C0
4+2 HP M/H/S Model 60 Stepping 3 C0
2+3 LP U/Y Model 69 Stepping 1 C0/D0

I'd say four dies for Alder Lake is the normal amount. That's why Meteor Lake is freaking me out with the sheer number of tape outs that they're planning.

 

[IntelUser2000]

Don't confuse Intel's myriad of SKUs and market segmentation strategies with actual dies. I only count 3 client dies for Haswell, although one of them did have two steppings:

4+3e HP H/R Model 70 Stepping 1 C0
4+2 HP M/H/S Model 60 Stepping 3 C0
2+3 LP U/Y Model 69 Stepping 1 C0/D0

I'd say four dies for Alder Lake is the normal amount. That's why Meteor Lake is freaking me out with the sheer number of tape outs that they're planning.

Those are actual dies. Not basing it off SKUs. I hate the trend of people claiming it's real when it's speculation. I'll say things like "I guess", "I speculate" when it's such.

Maybe they still do so, but I was surprised when they seemed to have pulled back on the modularity starting with Icelake.

 

[repoman27]

Those are actual dies. Not basing it off SKUs. I hate the trend of people claiming it's real when it's speculation. I'll say things like "I guess", "I speculate" when it's such.

Maybe they still do so, but I was surprised when they seemed to have pulled back on the modularity starting with Icelake.

The three I provided are the actual dies. I also included the Model and Stepping numbers from CPUID and hardware steppings from the sSpec listings. You can verify my information by checking the datasheets and ARK. What have you got to support your assertions?

I'm not trying to be a jerk here, but I am fairly certain there weren't 8 different Haswell client CPU die layouts.

 

[DrMrLordX]

In fact the yields will need to be higher not lower, cause the 130-140mm2 smallest die means they need to pump out 50%+ more wafers as they did in the Skylake generation.

Or they could just be sacrificing an even larger number of wafers than that (vs 22nm Haswell, not that I had brought 22nm into the discussion) due to yield problems. I'm a little surprised that anyone can assert without inside knowledge that 10SF and 10ESF are mature enough to have no considerable yield problems.

 

[jpiniero]

Speaking of Apple, they didn't spec bump the Intel Mac Pro to Icelake-W. Course Icelake-W is MIA despite getting 9 months old so who knows if any OEM will actually sell it.

 

[Doug S]

Speaking of Apple, they didn't spec bump the Intel Mac Pro to Icelake-W. Course Icelake-W is MIA despite getting 9 months old so who knows if any OEM will actually sell it.

Maybe this summer? I don't expect to see the ARM Mac Pro this year, so they might still need one more x86 kicker as that customer base is the most risk averse and there is probably sufficient appetite for customers who are leery of the 1.0 version of the ARM Mac Pro.

Of course that assumes Icelake-W ever sees the light of day.

 

[jpiniero]

Of course that assumes Icelake-W ever sees the light of day.

Yep, Apple might not need to release a new model because of it. Part of making a new model was probably because in normal circumstances the Cascade Lake-W processors would have started to become EOL by now. Obviously Intel can't if they don't have a replacement.

 

[ashFTW]

Maybe this summer? I don't expect to see the ARM Mac Pro this year, so they might still need one more x86 kicker as that customer base is the most risk averse and there is probably sufficient appetite for customers who are leery of the 1.0 version of the ARM Mac Pro.

Of course that assumes Icelake-W ever sees the light of day.

At this rate, Apple should release a Sapphire Rapids based x86 Mac Pro towards the end of this year. Releasing the ARM Mac Pro that runs circles around SPR-W would be awesome; beating 38 core based Icelake-W should be quite easy. Also they probably want to just do one final update, so SPR-W makes more sense, since it will have a longer shelf life.