Discussion Intel current and future Lakes & Rapids thread

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repoman27

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So bringing it back to Meteor Lake and what Intel has actually disclosed thus far, I was taking another look at this slide from the Intel Accelerated presentation:

Intel-Accelerated-2021-presentation-35.png

Intel specifically claimed Meteor Lake is made using second generation Foveros with a 36 µm bump pitch. That would point to them using "Intel 7 FOVEROS" for the base tile. During Architecture Day 2018, Intel showed a roadmap that included the following manufacturing processes:

127410nm CPU
1274.710+ CPU
1274.1110nm FOVEROS
1274.1210++ CPU
127510nm PCH
12767nm CPU

They then proceeded to rename nodes on a regular basis.

Hot Chips 31 2019:
1274.11 → 1274.FV​

Intel Architecture Day 2020:
10+ → 10nm SuperFin​
10nm FOVEROS → 10nm SuperFin FOVEROS​
10++ → 10nm Enhanced SuperFin​

Intel Accelerated 2021:
10nm Enhanced SuperFin → Intel 7​
7nm → Intel 4​

Intel Architecture Day 2021:
10nm SuperFin FOVEROS → Intel 7 FOVEROS​

All this is to say that "Intel 7 FOVEROS" is probably 1274.FV and best described as a Foveros optimized version of 10nm SuperFin that is close to Intel 7 but perhaps not quite as fully "Enhanced". The CNET photo of the partially populated Foveros test wafer shows us that this is a conventional Foveros design and not Foveros Omni. There is almost certainly active logic in the base tile, seeing as using a full-size silicon interposer with thousands of TSVs makes zero economic sense compared to EMIB, unless reducing the bump pitch from 55 µm to 36 µm was absolutely critical. Furthermore, the PCH had to go somewhere, and I highly doubt it was integrated into the SoC tile. I kind of get the impression that the PCH and CPU teams at Intel are working from totally different locations and have never actually met each other. A ~182 mm² die seems ridiculously large for just a 10nm PCH, a few thousand TSVs, and the additional plumbing to connect the top tiles, so there may be some cache in the base tile as well.

Nothing Intel has disclosed thus far would indicate more than three active tiles on top of the base tile, therefore the small tile adjacent to the CPU tile in the CNET photos most likely represents structural silicon. My measurements were pretty close to Locuza's, but I'd put the base tile at 16.8 mm x 10.85 mm = 182.28 mm² and the CPU tile at 4.8 mm x 7.9 mm = 37.92 mm². I figure the package to be 23 mm x 19 mm, which would make it Type4 or MTL-M. Intel has disclosed a 5-125 W TDP range for Meteor Lake, and 125 W seems a bit much for mobile, so that means Intel is working on both mobile and desktop processor lines under the Meteor Lake code name.

Because the actual CNET page is JavaScript hell, I'm also including some of the full-size images of Meteor Lake from that article here for reference:

Meteor Lake, powering PCs arriving in 2023, combines multiple chiplets into one larger processor using Intel's Foveros packaging technology. That stacks chiplets vertically and links them with high-speed data connections. Here, individual chiplets are bonded to a bottom base wafer layer made of uncut chips.

A 300mm wafer is studded with hundreds of Meteor Lake test chips. In this case, a top layer of chiplets is bonded to a base layer. Through a process called dicing, the wafer is then sliced into individual processors.

Meteor Lake, a PC chip due to ship in 2023, uses a second generation of Intel's Foveros technology to stack chiplets into a full processor. This Meteor Lake test vehicle is used to ensure the Foveros packaging is working correctly, with no alignment or electrical connection problems.

Meteor Lake test chips are squeezed side by side on a 300mm Intel wafer, with some processing elements individually bonded to others on the wafer's base layer below. This PC chip is due to ship in 2023. These are test chips to validate Intel packaging technology, not fully functioning processors.

Individual chiplets are visible in this closeup of Meteor Lake test chips.
 
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lobz

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That's true, CB and especially r23 seems to be a strong spot for ADL. The 5950x at 4.4GHz should still require a bit less power than the 12900k took to achieve 28k and the 5950x will score closer to 29k. One would be officially overclocked and the other unofficially :wink:. I think ADL-P has a good chance at beating Cezanne though once you get down to the 45W range or so and lower.
I'm pretty sure CB20&23 both love a big L2
 

lobz

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I can somewhat confirm this fact. A guy I know was considering moving back to Oregon (where he once lived) to work for a temp agency that was looking to place entry-level workers in one of Intel's facilities out there. Starting pay was maybe $18/hr? Granted that was about a year ago that he discussed it with me, so pay rate may have changed since then.
That's still a big pile of nothing considering how delicate the manufacturing process must be. Still, pharma fab workers make even less, and that's REALLY delicate... at least it should be 😂
 

lobz

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Cinebench fit into L2 caches before Alder Lake, an even bigger L2 won't make a difference.
If not the size itself, then something that's different in the hierarchy. I don't really know, of course :) I mean, Blender is not _that_ different of a workload, but the results differ enough that something must be different.
 

uzzi38

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If not the size itself, then something that's different in the hierarchy. I don't really know, of course :) I mean, Blender is not _that_ different of a workload, but the results differ enough that something must be different.
The difference is that at the stock 241W PL2 Alder Lake power throttles in Blender. It doesn't in Cinebench.

That's it.

EDIT: Added ComputerBase's results confirming the power throttling in Blender.


 
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repoman27

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I noticed that the versions of the Meteor Lake package rendering that are currently publicly available from Intel all appear to have somewhat redacted labels on the top tiles. The slide I posted previously shows the following labels:

CPU Tile
SOC Tile
GPU Tile

All of which are very generic and use the Intel preferred terminology of "tile" rather than "die" or "chiplet". Slides and screenshots posted by media outlets the day of the Intel Accelerated presentation showed slightly different labels for those tiles. According to the timestamp, VideoCardz posted this version of the slide slightly before the embargo lifted:



Here we see the tiles labeled as:

COMPUTE DIE
SOC - LP
GPU DIE (96 - 192 EUs)

"SOC - LP" would seem to indicate that this is a mobile variant, and that there is probably a corresponding "SOC - HP" for desktop processors. Compute and GPU are referred to as dies rather than tiles, and that may point to their nature as having been disaggregated from the SoC proper. The GPU die includes a range of EU counts. Seeing as this is a mobile processor, as indicated by the "SOC - LP", that range might only be applicable to the GT2 version of the GPU. Perhaps this is a bit of unintended disclosure by Intel, or simply reuse of an image that was designed to more specifically represent the mobile CPU package. At first I thought it might have been due to VideoCardz jumping the gun with some unofficial leaked slides, but WikiChip posted what appears to be a frame capture from the live webcast that included the same image:



Although this package rendering is highly stylized and not to scale, I do believe it may accurately represent the three active top tiles and their relative positioning in regards to MTL-M/P.

Taking the top tiles in turn, Intel has disclosed that the Meteor Lake CPU tile is being manufactured using the Intel 4 process and they even showed off a test wafer. Based on that, I calculated the die size to be 4.8 mm x 7.9 mm = 37.92 mm². I also made my own measurements of the CPU area of the ADL 8+8+1 HP die based on a high-resolution die shot and came up with 111.28 mm². Lopping off 4 Golden Cove performance cores to get a theoretical 4+8 configuration, which is what I think I'm seeing on the Meteor Lake CPU test wafer, yields an area of 69.11 mm². If we assume 2x density scaling for Intel 4 over Intel 7, that would shrink it down to 34.56 mm², which is a pretty good fit. Although we would expect Redwood Cove and Crestmont (if those code names are indeed correct) to be a bit fatter than Golden Cove and Gracemont, if the L3$ moved to the base tile, there would still be plenty of room for the cores to grow. MTL-P could ditch the little structural tile and use a longer 6+8 CPU tile. MTL-S would probably switch to a different base tile and SoC-HP tile and possibly use two of the 4+8 CPU tiles for an 8+16 configuration.

Despite what many folks are saying, the largest of the top tiles, the one in the middle, is the SoC tile. I measured that tile using the CNET photos and came up with 9.0 mm x 10.5 mm = 94.5 mm². If we take the ADL 8+8+1 HP die as an example and subtract the CPU and GPU areas, we get 209.1 - 111.28 - 12.31 = 85.51 mm² for "everything else", a.k.a. "SoC". And that's not including the sizable IPU and Thunderbolt 4 blocks typically present on mobile processors. So 94.5 mm² on Intel 7 might actually be cutting it rather fine. However, a recent report from the Taiwan based Commercial Times claims that not only will the GPU tile for Meteor Lake be manufactured on TSMC N3, but the SoC tile will be made using TSMC N5 or N4. Although this seems bonkers to me, it would give Intel a density increase of 1.66x or 1.76x respectively over using Intel 7 and probably offer considerable power savings to boot. This may even be necessary due to additional area requirements resulting from disaggregation. In keeping with historical precedent, it's also possible that the SoC-HP tile will forgo integrated Thunderbolt and IPU and instead include a 64 EU GT1 GPU, obviating the requirement for a separate GPU tile.

Finally, the long skinny tile is the GPU tile, housing 192 Gen12 EUs manufactured on TSMC N3. My measurements of this tile based on the CNET photos came in at a troublingly small 2.25 mm x 10.5 mm = 23.625 mm². Going back to the ADL 8+8+1 HP die and measuring the 32 EU GT1 slice, I came up with an area of 12.31 mm². However, I realized that a more apt comparison is the 96 EU GT2 GPU from the TGL 4+2 LP die, which is still Gen12 but uses a denser layout to achieve an area of just 32.72 mm² on 10nm SuperFin. Doubling the number of EUs on TSMC N3 which offers 2.83x density would result in an area of 23.12 mm². That would just barely fit given my die measurements, but would have some room to breathe if Locuza's estimate of 2.6 mm x 11.0 mm = 28.6 mm² turns out to be closer to the actual dimensions. One final possibility is that the SoC-LP tile includes 64 EUs and the GPU tile is simply an additional 128 EU slice used for GT2 configurations, although that strikes me as unlikely.
 
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mikk

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TSMC 3nm is doubtful, why do they need TSMC 3nm for 192 EUs? Don't you think 5nm is a better fit around Q2 2023 (capacity, cost)? AMD won't have 3nm in the middle of 2023 if they are about to launch first 5nm CPUs at the end of 2022. Furthermore Meteor Lake for desktop is unlikely now and not needed given that Arrow Lake is supposedly coming in Q4 2023 on a newer architecture. The 4+8 Meteor is a sign they are not ready fo a high core count and it's questionable if they can hit 5 Ghz on this new node so early. It's fine for mobile, they can replace 2+8/4+8 15-28W ADL-P with a more energy efficient CPU and they don't neccessarily need 4.5-5 Ghz in this low power segment. All of the initial EUV volume goes into mobile. At the end of 2023 we might see a limited Arrow Lake release for the desktop 1 year after Raptor Lake-S, like they did with ADL-S this year.
 

repoman27

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Why would Intel possibly tape out a design scheduled for retail in 2023 on a legacy node? If wafer starts are available on N3, it offers the cheapest transistors (highest available density) and best power/performance. Unless the cost per yielded wafer increases more than transistor density, the leading edge node will always give you the most transistors for your dollar. Intel can simply buy back their process advantage over AMD, and you're actually questioning why they would do so?

A hell of a lot more people will happily pay for a laptop with a 192 EU IGP and decent battery life than a desktop PC with a discrete GPU. Why would the GPU tile be a separate die unless it was on a different process than the SoC tile?

Why do you think Meteor Lake will arrive later than Q1'23 and Arrow Lake in Q4'23? Do we have any corroboration on that or just the single post in this thread? Why would Intel publicly say MTL desktop is a thing 4 months ago if it wasn't still POR?

The 4+8 Meteor Lake CPU tile is also for 5-9W MTL-M, I would still expect a 6+8 CPU die for the P-series in the 28-45W range. Is 4+8 a sign that Intel isn't ready for high core count, or is it a sign that they've finally embraced chiplets? Was an 8-core Zen CCD a sign that AMD wasn't ready for high core count processors, or an indication that they could scale to pretty much any number of cores you were willing to pay for once they were no longer constrained by monolithic dies? Also, the CPU tile is on Intel 4 not TSMC N3, almost certainly because Intel thinks their process will clock higher out the gate for those cores.
 

diediealldie

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TSMC 3nm is doubtful, why do they need TSMC 3nm for 192 EUs? Don't you think 5nm is a better fit around Q2 2023 (capacity, cost)? AMD won't have 3nm in the middle of 2023 if they are about to launch first 5nm CPUs at the end of 2022. Furthermore Meteor Lake for desktop is unlikely now and not needed given that Arrow Lake is supposedly coming in Q4 2023 on a newer architecture. The 4+8 Meteor is a sign they are not ready fo a high core count and it's questionable if they can hit 5 Ghz on this new node so early. It's fine for mobile, they can replace 2+8/4+8 15-28W ADL-P with a more energy efficient CPU and they don't neccessarily need 4.5-5 Ghz in this low power segment. All of the initial EUV volume goes into mobile. At the end of 2023 we might see a limited Arrow Lake release for the desktop 1 year after Raptor Lake-S, like they did with ADL-S this year.
Intel can block both Apple and AMD together by buying an N3 process node from TSMC. Just look at the M1 Max. It has an extremely huge iGPU. Apple knows that iGPU affects UX a lot, especially for light users. To repel this threat, it's important to introduce sub-dGPU level iGPUs. Intel 4 capacity will not be enough.

Meanwhile, N3 used by AMD can pose a great threat to Intel's server market(which is already in danger). AMD is using superior designs now, and due to the increase in sales volume, AMD could try using leading-edge nodes for high-value markets in near future. Buying N3 capacity will give intel better mobile products while keeping CPU competition in sub-edge nodes, hiding CPU manufacturing process inferiority.
 

DrMrLordX

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Intel can block both Apple and AMD together by buying an N3 process node from TSMC.
Not if TSMC only sells them 20 wkpm from that node, tops. TSMC is interesting in fulfilling the orders of their most-loyal customers, and they have repeatedly stated publicly that they will not solve all of Intel's manufacturing problems for them.
 

diediealldie

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Not if TSMC only sells them 20 wkpm from that node, tops. TSMC is interesting in fulfilling the orders of their most-loyal customers, and they have repeatedly stated publicly that they will not solve all of Intel's manufacturing problems for them.
TSMC will not solve all of Intel's problems so Intel solved some of its problems on its own. Even if Intel wasn't able to buy all of 3nm capacity, more wafer bought means fewer leading-edge products from its competition due to EUV shortages.
Anyway, 20 kwpm will be enough to cover Intel's laptop iGPU lineup.
 

DrMrLordX

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TSMC will not solve all of Intel's problems so Intel solved some of its problems on its own. Even if Intel wasn't able to buy all of 3nm capacity, more wafer bought means fewer leading-edge products from its competition due to EUV shortages.
Since when did TSMC have problems getting EUV equipment?
 

diediealldie

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Since when did TSMC have problems getting EUV equipment?
Everyone has trouble getting EUV equipment. Unlike Intel who doesn't know how to use it, TSMC and Samsung are not getting enough EUVs. According to ASML, each 45k wpm requires 10~20 EUV scanner for 7~5nm nodes(3nm will need more), but ASML makes ~30 EUV scanners every year(Plans to boost to 60 by 2023 but not here yet).
So each year, ASLM can supply 100k wpm EUV fabs worldwide. The world lacks 15 EUV scanners in 2022 according to the source. Since Samsung bought more EUV than TSMC in 1st half of 2021, we can't say that TSMC got sufficient EUV by buying every EUV possible.

And now, DRAM makers are starting to purchase EUVs(2~10(?!) EUVs per 100kwpm) . In DUV days, TSMC alone had 100k~120k wpm for each leading-edge nodes. But now, that 100k will be separated to TSMC, Samsung and later, Intel.
 

eek2121

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"SOC - LP" would seem to indicate that this is a mobile variant, and that there is probably a corresponding "SOC - HP" for desktop processors. Compute and GPU are referred to as dies rather than tiles, and that may point to their nature as having been disaggregated from the SoC proper. The GPU die includes a range of EU counts. Seeing as this is a mobile processor, as indicated by the "SOC - LP"
If current leaks about ADL-P are any indication, laptops are going to be the cause of most excitement moving forward.
 

mikk

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Why would Intel possibly tape out a design scheduled for retail in 2023 on a legacy node?

You are aware that AMDs mobile series 7000 is going to use TSMC 5nm in 2023 and that the first GPUs next year are 6nm based including AMDs next gen Navi? TSMC 5nm has a long way to go.

Why do you think Meteor Lake will arrive later than Q1'23 and Arrow Lake in Q4'23? Do we have any corroboration on that or just the single post in this thread? Why would Intel publicly say MTL desktop is a thing 4 months ago if it wasn't still POR?

I'm not ruling out a late Q1 2023 start (launch), actually Raichu implied late Q1 is possible. However Q2 is a safer bet and the Roadmap leak said Q2: https://videocardz.com/newz/intel-arrow-lunar-and-nova-lake-codenames-appear-in-a-leak-as-meteor-lake-successors

Also, the CPU tile is on Intel 4 not TSMC N3, almost certainly because Intel thinks their process will clock higher out the gate for those cores.
Intels CPU design might not be ready to use other foundrys and using TSMC for everything can be a challenge when it comes to Intels mobile volume. Arrow Lake in Q4 2023 is an Intel 3 (the old 7+) candidate which is probably a better fit for high clocking desktop parts.
 

uzzi38

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Intel can block both Apple and AMD together by buying an N3 process node from TSMC. Just look at the M1 Max. It has an extremely huge iGPU. Apple knows that iGPU affects UX a lot, especially for light users. To repel this threat, it's important to introduce sub-dGPU level iGPUs. Intel 4 capacity will not be enough.

Meanwhile, N3 used by AMD can pose a great threat to Intel's server market(which is already in danger). AMD is using superior designs now, and due to the increase in sales volume, AMD could try using leading-edge nodes for high-value markets in near future. Buying N3 capacity will give intel better mobile products while keeping CPU competition in sub-edge nodes, hiding CPU manufacturing process inferiority.
What makes you think Intel would have higher priority for leading edge nodes at TSMC than AMD?
 
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uzzi38

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You are aware that AMDs mobile series 7000 is going to use TSMC 5nm in 2023 and that the first GPUs next year are 6nm based including AMDs next gen Navi? TSMC 5nm has a long way to go.
Mobile using N5 in 2023 is just how timelines worked out. Zen 4 based designs aren't ready for mass production ahead of Q1 2022, Zen 3 is.

As for the GPU side, that's an adv. packaging validation constraint, not a node constraint. Genoa will almost certainly be GA by mid-way through next year given that it had already been sampling for a while now, and even for RDNA3 Navi31 has already taped out, while Navi33 tapes out early next year. Navi33 only comes to market first because it's easier to bring it to market.
 
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uzzi38

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I still think Intel buying the N3 capacity that Apple didn't need right away was part of the deal.
Part of what deal? And why?

Apple isn't using N3 until 2024. So what N3 capacity are you referring to when you say any of this?
 

repoman27

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You are aware that AMDs mobile series 7000 is going to use TSMC 5nm in 2023 and that the first GPUs next year are 6nm based including AMDs next gen Navi? TSMC 5nm has a long way to go.
Tell that to Apple who have already shipped:

200 million A14 @ 87.76 mm²
80 million A15 @ 107.7 mm²
20 million M1 @ 119 mm²
2 million M1 Pro @ ~250 mm²
1 million M1 Max @ ~424 mm²

All made on TSMC N5.

I'm not ruling out a late Q1 2023 start (launch), actually Raichu implied late Q1 is possible. However Q2 is a safer bet and the Roadmap leak said Q2: https://videocardz.com/newz/intel-arrow-lunar-and-nova-lake-codenames-appear-in-a-leak-as-meteor-lake-successors
That article's sole source is this thread. Do we have any corroboration on that info?

Intels CPU design might not be ready to use other foundrys and using TSMC for everything can be a challenge when it comes to Intels mobile volume. Arrow Lake in Q4 2023 is an Intel 3 (the old 7+) candidate which is probably a better fit for high clocking desktop parts.
I'm pretty sure Intel's highest volume product ever was the iPhone modem, and they got out of that business entirely. Intel doesn't have any true "mobile" design wins, which means notebook PC platforms are currently their highest volume product. Apple bought more N5 wafers from TSMC this year than Intel would require to produce 100% of their client platforms—granted they also accounted for a little over 25% of TSMC's total revenue.

TSMC has 3x the fab capacity of Intel. Intel will never be able to buy 100% of TSMC's capacity at the leading edge because they have neither the money nor the customers for that much silicon. However, seeing as every fab is capacity constrained at the moment, simply bidding on wafer starts might serve to drive up costs for Intel's competitors, which could be viewed as an upside. Intel buying back their process advantage is also somewhat problematic because as they shift their higher-volume products to TSMC, their own fabs will quickly go from capacity constrained to underutilized. Unless Intel can find foundry customers to take up that slack, their fabs will become multi-billion dollar abatrosses on their balance sheet.
 

repoman27

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That's the complete opposite of the data from the Mizuho report.
No it's not. Read the actual report. It's a buy rating for ASML because:
EUV business remains solid and strong for ASML in the next five years due to rising EUV mask layer adoption.
ASML’s EUV shipments will increase to 55 systems in 2023 from 50 systems in 2022, per our estimate.

KNOW: Both shipments and ASP increase for EUV system business
We expect the number of EUV mask layers to increase 80%-90% for 3nm (vs.
5nm) and around 50% for 2nm (vs. 3nm). This could further lead to higher EUV
requirement per capacity during 2021-25. We forecast EUV ASP to increase 5%
YoY in 2022 and 6% in 2023 due to higher shipments for advanced EUV system
(NXE: 3600D, NXE: 3800E).
That report never once addresses whether any of TSMC's customers were underinvesting in EUV or would be more significantly impacted by supply constraints on EUV lithography equipment. TSMC may have half of all EUV systems installed to date, but that's only because they have a lot more processes using EUV doing a lot more volume than anyone else.
 

uzzi38

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2023 Macs and then the 2023 iPhone.
What makes you think either will be N3? They're skipping N3 in 2022 because of poor power/perf and density shrink relative to cost increase, especially compared to N4P. N3E is only going to be ready at the end of 2023/beginning of 2024, and so misses the production cycle for 2023 iPhone.
 

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