Discussion Intel current and future Lakes & Rapids thread

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mikk

Diamond Member
May 15, 2012
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I assumed that the compute tile would be at least 6+8 to maintain parity with ADL-P, but I think you could be right. The more I look at this wafer shot, the more I think it is 4P+8E:

View attachment 53082

This is a conservative approach from Intel which isn't new. The cancelled Cannonlake-U was a 2C version, Broadwell was 2C. All the last CPUs on a new Intel process were conservative. This low core count (even if there is a 6+8 version) is also a strong hint it's mobile only. They obviously won't/can't go down from 8+8/8+16 in the desktop.

They (theoretically) could use the older Intel 7 for the iGPU, maybe this is an option for the 96EU version, this is a cheap alternative why not. As for the 192 EU version I don't think so, to fully make use of 192 EUs they also need efficiency improvements on the process side, be it Intel 4 or TSMC 3nm/5nm. It's a bit of a waste if they don't have efficiency gains over Intel 7. I would guess they have another 2x performance improvement target over TGL-U or even ADL-P 96 EUs just like ICL-U over CML-U and TGL-U over ICL-U.
 

TESKATLIPOKA

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May 1, 2020
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OK, let's do the math here.

Given a 2.6 mm x 11.0 mm die, you can obtain 2177 dies per 300 mm wafer. If TSMC N3 defect densities follow the trend established by N7 and N5, we would expect around 0.11 defects per cm² at the beginning of the HVM ramp. Using the Seeds model, a 28.6 mm² die would see a yield rate of 96.95%, or 2110 fully functional dies per wafer. At a cost of $20,500 per finished wafer, each GPU die would cost Intel $9.72.

Just the GPU slice (not including media block or display engine) for ADL 8+8+1 is 16.64 mm². That's for 32 EUs on Intel 7, so 192 Gen12 EUs would work out to ~100 mm². You can fit 626 9.0 mm x 11.0 mm dies on a 300 mm wafer. A 99 mm² die and a D0 of 0.10 would result in a 90.99% yield rate, or 569 fully functional dies per wafer. A finished Intel 7 wafer would have to cost $5,500 or less to compete with TSMC N3.

Notebook PC platforms are Intel's iPhone. They generate more revenue and profit for Intel than any other product they produce. Intel currently has locked in customers for ~130 million U Series chips with IGPs annually vs. 0 for desktop discrete GPUs. A best case scenario for Intel would be reaching something like 8 million dGPUs in 2023. The first Arc products, slated to ship in Q1'22, are based on the Alchemist GPU which is being manufactured on TSMC N6. It is incredibly unlikely that the follow up, Battlemage, will be a Q1'23 product made entirely on TSMC N3. However, a 192 EU tile at just 28.6 mm² that could be used for both IGPs and dGPUs is a perfect lead-off product on a new manufacturing node.
Is the difference in density really 3x better?

edit: Ok, I found this, and It could be about 3x better.
 
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ashFTW

Senior member
Sep 21, 2020
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Jeezy Pete, that CNET article has amazing photos of the SPR substrate in both unpopulated and populated states. The SPR XCC compute tiles are 426.4 mm². There are two because there is a left and right that have floor plans that are essentially mirror images, but they are the same dimensions. The only tile between the compute tiles and the HBM2E stacks is the EMIB, which is embedded in the organic substrate.

edit: The green solder mask covers the top layer of the PCB and EMIB dies, but there's only a single EMIB die linking each compute tile to its HBM stack, and five EMIB dies linking each compute tile to its neighbors.


You are wrong. I will detail it when I have time.
 

repoman27

Senior member
Dec 17, 2018
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It easily would be. That's the upside of being an IDM.
Let's say that it is, because it actually could be in the right ballpark for Intel's loaded wafer cost. So that means using TSMC N3 isn't necessarily more expensive than using Intel 7, which addresses the primarily area based financial argument. Now let's turn to the power and performance arguments...

@Exist50, don't forget that despite the name changes, we're comparing the density of Intel 10nm to TSMC 3nm here. And I know that the nm numbers are irrelevant, but we're essentially looking at 100.8 MTr/mm² vs. 285.3 - 291.2 MTr/mm², or very nearly a 3x scaling.
 

naukkis

Senior member
Jun 5, 2002
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@Exist50, don't forget that despite the name changes, we're comparing the density of Intel 10nm to TSMC 3nm here. And I know that the nm numbers are irrelevant, but we're essentially looking at 100.8 MTr/mm² vs. 285.3 - 291.2 MTr/mm², or very nearly a 3x scaling.
And even Intel could use that transistor density to something profitable instead of GPU of their mainstream cpu.... like server CPU which have 3x cores.
 

jpiniero

Lifer
Oct 1, 2010
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Let's say that it is, because it actually could be in the right ballpark for Intel's loaded wafer cost.
The cost to Intel now is basically like 200-300 bucks tops. You won't see that on the accounting because they are including money Intel spent 5 years ago.
 

eek2121

Golden Member
Aug 2, 2005
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Let's say that it is, because it actually could be in the right ballpark for Intel's loaded wafer cost. So that means using TSMC N3 isn't necessarily more expensive than using Intel 7, which addresses the primarily area based financial argument. Now let's turn to the power and performance arguments...

@Exist50, don't forget that despite the name changes, we're comparing the density of Intel 10nm to TSMC 3nm here. And I know that the nm numbers are irrelevant, but we're essentially looking at 100.8 MTr/mm² vs. 285.3 - 291.2 MTr/mm², or very nearly a 3x scaling.
Intel 4 is absolutely comparable to edge TSMC nodes. Transistor density on Intel 4 is higher than TSMC N5.

Transistor density on Intel 7 can be comparable with TSMC N7.

And even Intel could use that transistor density to something profitable instead of GPU of their mainstream cpu.... like server CPU which have 3x cores.
You guys talking about cost bugs me. Go look at TSMC’s financials, specifically, margins. Intel’s costs are far below what TSMC charges customers. Intel is vertically integrated.

Intel’s biggest worry for the forseeable future is their lack of EUV machines. They control the majority of everything else. They make more money per chip than AMD does. They don’t have the supply constraints AMD does (this isn’t to say they don’t have supply issues, but they don’t compete with others for a given node).

The only reason Intel is using TSMC is due to EUV. Intel did not order enough EUV machines, which limits the number of chips they can make on Intel 4 and below. They are working to rectify that going forward.
 

Accord99

Platinum Member
Jul 2, 2001
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The only reason Intel is using TSMC is due to EUV. Intel did not order enough EUV machines, which limits the number of chips they can make on Intel 4 and below. They are working to rectify that going forward.
Assuming that TSMC remains capacity limited for its most cutting edge node, it could also be a competitive move. One 3nm TSMC wafer for Intel is one less wafer for AMD/Apple/Nvidia/Qualcomm/etc.
 

DrMrLordX

Lifer
Apr 27, 2000
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The only reason Intel is using TSMC is due to EUV.
Assuming all is well with Intel 7nm/Intel 4 then I guess so? It's not clear whether Intel 4 is really comparable to TSMC N3 in density and performance. I would think products fabbed on N5P in particular could trade blows with Intel 4. Intel's problem is that they aren't shipping anything on Intel 4 yet, while TSMC has been in full production on N5 and N5P for awhile.

We also aren't touching on yields for Intel 4. It is unlikely that Intel will have the same problems with 7nm/Intel 4 that they did with 10nm but still. Just because Gelsinger and company swear up and down that Intel 4 products will ship in 2023 no problem, doesn't absolutely mean that's the case. Taking wafers of TSMC N3 is a way of hedging against potential failure, among other things.
 
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AMDK11

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Jul 15, 2019
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I wonder why Intel did not disclose the scheduler and GoldenCove physical registry file and LOAD / STORE bandwidth. Could this data be disclosed with the premiere of SapphireRapids?
 

JoeRambo

Golden Member
Jun 13, 2013
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I wonder why Intel did not disclose the scheduler and GoldenCove physical registry file and LOAD / STORE bandwidth. Could this data be disclosed with the premiere of SapphireRapids?
Load BW is disclosed to be 3x256 or 2x512.
Store is most likely 2x256
 

coercitiv

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Jan 24, 2014
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My Thread Dictator™ joke is slowly coming to life.
Aaaaand... it's here!

Gigabyte releases DRM Fix Tool for Intel Alder Lake processors
Users can easily control the status of the E-cores through the UI of this utility without any complicated installation. GIGABYTE’s DRM Fix Tool provides a much easier solution to the DRM issue compared to other solutions which require adjusted BIOS settings, PS/2 keyboard connection, or even exclusive button on the chassis and keyboard.
 

JoeRambo

Golden Member
Jun 13, 2013
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Any chance this tool will work on any Alder Lake system? Kinda annoying that Intel did not release a universal tool for this purpose.
Says requires BIOS support, so probably specific to Gigabyte ADL motherboards with newest BIOS. No worries, other vendors have other tricks, like Scroll Lock etc.
 
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repoman27

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Dec 17, 2018
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The cost to Intel now is basically like 200-300 bucks tops. You won't see that on the accounting because they are including money Intel spent 5 years ago.
You realize that $200-300 is on the low side for just the cost of the raw wafer and consumables, right? Even if all of Intel's 10nm equipment and facilities were 100% depreciated at this point, which they are not, the loaded cost would still include labor, facility operating costs and maintenance. Yields on 10nm (Intel 7) appear to be OK at this point, but the process still involves copious multi-patterning which leads to long cycle times. Throughput and yields will never be able to match 14nm, so it will always be a more expensive node. I challenge you to find a credible analyst who would peg the Intel 7 yielded wafer cost in Q4'21 at less than $3000.

Intel 4 is absolutely comparable to edge TSMC nodes. Transistor density on Intel 4 is higher than TSMC N5.

Transistor density on Intel 7 can be comparable with TSMC N7.
Yes, Intel 4 will be more dense than TSMC N5. However, TSMC N3 will be 1.4x denser and enter HVM right around the same time as Intel 4. N5 products have been shipping in high volume for over a year, and 430 mm² monolithic SoCs are available today. In terms of process maturity, Intel 7 is up against TSMC N5/N5P which is 1.65x denser.

You guys talking about cost bugs me. Go look at TSMC’s financials, specifically, margins. Intel’s costs are far below what TSMC charges customers. Intel is vertically integrated.

Intel’s biggest worry for the forseeable future is their lack of EUV machines. They control the majority of everything else. They make more money per chip than AMD does. They don’t have the supply constraints AMD does (this isn’t to say they don’t have supply issues, but they don’t compete with others for a given node).

The only reason Intel is using TSMC is due to EUV. Intel did not order enough EUV machines, which limits the number of chips they can make on Intel 4 and below. They are working to rectify that going forward.
If TSMC N3 and Intel 4 were to have equivalent yielded wafer costs, a TSMC gross margin of 30% would still provide Intel with the same transistor cost. Overall, TSMC's gross margins are currently hovering above 51%, but the margins on the bleeding edge nodes are almost certainly lower. And because TSMC is way higher volume, generally has lower operating costs, and has had better yields recently than Intel, their yielded wafer costs will likely be lower than Intel's. So the price difference isn't going to be all that much in the end. Being an IDM doesn't mean you get your fabs for nothing and your wafers for free. It's also darn near impossible to make leadership products if you aren't using the best available process, which is why Intel killed it for over a decade when they had a monopoly on manufacturing that was way ahead of what everyone else had.

Intel 4 will be Intel's first manufacturing process to use EUV, and it won't enter HVM until H2'22. It will use EUV lithography for 12 layers. Intel will have 12-16 EUV machines installed up and running by then, enough to easily accommodate 45K WSPM. Thus far, they have only taped out a single 38 mm² client compute tile on that node, and announced that the Granite Rapids server parts, ostensibly due out by the end of 2023 will also use Intel 4 in some capacity. So while everyone on the internet keeps parroting that Intel is constrained by a lack of EUV equipment, I see $2B worth of EUV machines sitting around depreciating while utilization is nowhere near at full capacity.

The Mizuho Securities note that everyone uses as evidence of Intel's shortage of EUV equipment was a buy rating for ASML, and never once insinuated that Intel was underinvesting. That might have started with Daniel Nenni over at SemiWiki.
 

jpiniero

Lifer
Oct 1, 2010
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You realize that $200-300 is on the low side for just the cost of the raw wafer and consumables, right? Even if all of Intel's 10nm equipment and facilities were 100% depreciated at this point, which they are not, the loaded cost would still include labor, facility operating costs and maintenance.
IIRC fab workers don't make that much and the operating costs are otherwise not much at 100% utilization. The 'cost' of a wafer is basically paying off the tools and the fab space. But they already spent the money on the tools a long time ago presumably and they are using the fab space intended for 7 nm. It's going to be very cheap to run once you factor in the money already spent. As much of a disaster 10 nm has been they need to keep it running at 100% for a long time too.

The Mizuho Securities note that everyone uses as evidence of Intel's shortage of EUV equipment was a buy rating for ASML, and never once insinuated that Intel was underinvesting. That might have started with Daniel Nenni over at SemiWiki.
Now 7 nm is a different story. My feeling is that Intel was on the fence as to whether to continue with it (and wasn't going to pull the trigger) until someone at Intel got the bright idea to use the threat of the Chinese invasion of Taiwan as an excuse to get the US Govt to subsidize it.

Any I4 supply is presumably the R&D production fab only.
 

repoman27

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Dec 17, 2018
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IIRC fab workers don't make that much and the operating costs are otherwise not much at 100% utilization. The 'cost' of a wafer is basically paying off the tools and the fab space. But they already spent the money on the tools a long time ago presumably and they are using the fab space intended for 7 nm. It's going to be very cheap to run once you factor in the money already spent. As much of a disaster 10 nm has been they need to keep it running at 100% for a long time too.
Just keeping the lights on costs more than you might think. Here's an example of IC Knowledge's estimate for TSMC 28nm in Q1'14:



Yielded wafer cost is $2813.59 with $1565.29 of that being depreciation. Costs jumped significantly with FinFET and again with multi patterning. Longer cycle times and higher defect rates translate directly into higher wafer costs. Also, depreciation is typically calculated on a 5-year straight line for equipment and 10-year for facilities based on the date they are available for service. Intel's capital investments in Arizona and Israel have been significant and ongoing. There's no way Fab 42 and every piece of equipment sitting inside it is fully depreciated. Furthermore, Intel's operating and labor costs in Oregon, Arizona, and Israel are likely higher than TSMC's are in Taiwan.

Part of the reason Intel went for 2.7x scaling with 10nm was to offset the increase in wafer costs due to SAQP in an attempt to maintain the transistor cost trend predicted by Moore's law.
 

maddie

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Jul 18, 2010
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IIRC fab workers don't make that much and the operating costs are otherwise not much at 100% utilization. The 'cost' of a wafer is basically paying off the tools and the fab space. But they already spent the money on the tools a long time ago presumably and they are using the fab space intended for 7 nm. It's going to be very cheap to run once you factor in the money already spent. As much of a disaster 10 nm has been they need to keep it running at 100% for a long time too.



Now 7 nm is a different story. My feeling is that Intel was on the fence as to whether to continue with it (and wasn't going to pull the trigger) until someone at Intel got the bright idea to use the threat of the Chinese invasion of Taiwan as an excuse to get the US Govt to subsidize it.

Any I4 supply is presumably the R&D production fab only.
Using your arguments as to costs would imply that TSMC should be making a LOT more than they are, unless you're also implying that Intel has some secret for cheap manufacturing.
 
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Doug S

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Yes, Intel 4 will be more dense than TSMC N5. However, TSMC N3 will be 1.4x denser and enter HVM right around the same time as Intel 4. N5 products have been shipping in high volume for over a year, and 430 mm² monolithic SoCs are available today. In terms of process maturity, Intel 7 is up against TSMC N5/N5P which is 1.65x denser.
N3 is 1.7x as dense as N5, not 1.3x. For logic, at least...

Comparing the claimed transistor densities of different fabs is pointless, as those are basically marketing numbers. There is no standard of what kind of chip they use, or even how they COUNT transistors. David Kanter has a great writeup of the folly of such comparisons here.
 

repoman27

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N3 is 1.7x as dense as N5, not 1.3x. For logic, at least...

Comparing the claimed transistor densities of different fabs is pointless, as those are basically marketing numbers. There is no standard of what kind of chip they use, or even how they COUNT transistors. David Kanter has a great writeup of the folly of such comparisons here.
Right, you missed the comma there and got the number wrong, but whatever. What I was saying was, "TSMC N3 will be 1.4x denser and enter HVM right around the same time as Intel 4."

And I'm not comparing marketing numbers. I'm comparing fairly rigorously obtained values for MTr/mm² provided by David Schor over at WikiChip, which are based on the actual dimensions of two specific standard cells. That being said, Intel's claims regarding Intel 4 density have been inconsistent and somewhat vague thus far, but they haven't said anything publicly that would lead me to expect less than 200 MTr/mm².
 
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DrMrLordX

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IIRC fab workers don't make that much
I can somewhat confirm this fact. A guy I know was considering moving back to Oregon (where he once lived) to work for a temp agency that was looking to place entry-level workers in one of Intel's facilities out there. Starting pay was maybe $18/hr? Granted that was about a year ago that he discussed it with me, so pay rate may have changed since then.
 
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