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Intel Comet Lake Thread

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DrMrLordX said:
Seems a bit fishy due to the spoofed email address and it's a new source. But it would make sense.
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Sunny would be weird since even the mobile version would be released around/after Tigerlake is. And also, a Sunny core is 6.91 mm2 on 10 nm so a 10 core 14 nm die would start to get really big.
 
jpiniero said:
Sunny would be weird since even the mobile version would be released around/after Tigerlake is. And also, a Sunny core is 6.91 mm2 on 10 nm so a 10 core 14 nm die would start to get really big.
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Definitely. Willow Cove would (presumably) be even bigger. Intel is all about that advanced packaging tech, though. If they could figure out the thermals, they could stack some chips or, you know, something something Foveros EMIB <insertbuzzwordhere> I don't know.
 
Sunnycove was initially on 14nm. If it is in Rocketlake it won't have AVX512.

I think Cometlake-S will have Tigerlake-S(10nm++(1274.12)) on the same(LGAxxxxv1) platform: PCIe3/USB3.2 platform. With Rocketlake-S and Alderlake-S(10nm+++(1274.1y)) will be on the second(LGAxxxxv2) platform: PCIe4/USB4 platform.
 
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jpiniero said:
If you were hoping that Comet Lake Pentium would be 4C4T, doesn't look like it.
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A bit disappointing to me to be to be sure. An $60-80 4C/8T 4.1Ghz with 4.5Ghz 1C turbo, would have made a decent little "budget gamer" base chip. Maybe even un-throne the Ryzen R5 3500 (or 3500, or 3500X, if those even ever show up in the USA).
 

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Comet Lake U Pentium and Celeron announced. Stingy Intel didn't even give the Pentium a turbo boost so the gap is so wide between it (2.4) and the i3 (which can boost to 3.7 on both cores and 4.1 on one). Talk about Trash bin chips.
 
jpiniero said:
Comet Lake U Pentium and Celeron announced. Stingy Intel didn't even give the Pentium a turbo boost so the gap is so wide between it (2.4) and the i3 (which can boost to 3.7 on both cores and 4.1 on one). Talk about Trash bin chips.
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I dont't even know why they both to go to such R&D lengths / expenses, if they're just going to turn around and heavily gimp the chips before they make it to market. I mean, really Intel???.
 
VirtualLarry said:
I dont't even know why they both to go to such R&D lengths / expenses, if they're just going to turn around and heavily gimp the chips before they make it to market. I mean, really Intel???.
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I imagine it's exclusively chips that wouldn't pass the 10100U specs. But it does feel really stingy.
 
VirtualLarry said:
I dont't even know why they both to go to such R&D lengths / expenses, if they're just going to turn around and heavily gimp the chips before they make it to market. I mean, really Intel???.
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It shouldn't cost them much, if anything. They design their chips with it in mind. Most of features such as VT, AVX, and HT can be fused off. Clock doesn't even have to be binned anymore since its multiplier locked on the non-K chips. It'll be even easier for the Pentium and Celerons to pass working/not working since you can set the frequency so low.

Sometimes the particular market demands the chip so manufacturers are forced to disable cores just to cater to them. Now Intel seems flexible enough that they can simply cut cores in design and quickly make a new mask with smaller dies. At one point they had 6-7 different dies for the Atoms, and it was more than 5 years ago. If they were individually designing them they would never be able to do that.

So making a new die isn't difficult as long as its based off a common design. You just cut cores/caches out. It's same with their Gen graphics. Every year they talk about modularity. Ring/Mesh has to do with this as well. Crossbar interconnections used in older chips like the Nehalem was not conducive to adding/deleting cores.
 
IntelUser2000 said:
So making a new die isn't difficult as long as its based off a common design. You just cut cores/caches out. It's same with their Gen graphics. Every year they talk about modularity. Ring/Mesh has to do with this as well. Crossbar interconnections used in older chips like the Nehalem was not conducive to adding/deleting cores.
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That's a benefit to the Ring/Mesh that I hadn't really considered before, such as core/design modularity, thanks for bringing that to my attention.
 
It's not a dual core native design - There's obviously a 6 core die, and I believe there might be a native quad core too, and the Celeron and Pentium are just the defective ones where only 2 cores work.
 
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